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1. 发明授权

US07023061B2 Memory transistor array utilizing insulated word lines as gate electrodes 失效
标题翻译：使用绝缘字线作为栅电极的存储晶体管阵列
公开(公告)号：US07023061B2
公开(公告)日：2006-04-04
申请号：US11072505
申请日：2005-03-07
申请人： Kazumasa Nomoto , Toshio Kobayashi , Akihiro Nakamura , Ichiro Fujiwara , Toshio Terano
发明人： Kazumasa Nomoto , Toshio Kobayashi , Akihiro Nakamura , Ichiro Fujiwara , Toshio Terano
IPC分类号： H01L29/76
CPC分类号： H01L27/11568 , H01L21/2815 , H01L27/115 , H01L29/6656
摘要： A semiconductor device enabling word lines to be arranged at close intervals, comprising a plurality of memory transistors arranged in an array and a plurality of word lines serving also as gate electrodes of memory transistors in a same row, extending in a row direction, and repeating in a column direction, where insulating films are formed between the plurality of word lines to insulate and isolate the word lines from each other and where a dimension of separation of word lines is defined by the thickness of the insulating films.
摘要翻译：一种半导体器件，其能够以近似的间隔布置字线，包括排列成阵列的多个存储晶体管，以及同时作为沿行方向延伸的同一行中的存储晶体管的栅电极的多条字线，并重复在列方向上，在多个字线之间形成绝缘膜以使字线彼此绝缘和隔离，并且字线分隔的尺寸由绝缘膜的厚度限定。

2. 发明授权

US07227255B2 Semiconductor device and method of producing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07227255B2
公开(公告)日：2007-06-05
申请号：US11098501
申请日：2005-04-05
申请人： Kazumasa Nomoto , Toshio Kobayashi , Akihiro Nakamura , Ichiro Fujiwara , Toshio Terano
发明人： Kazumasa Nomoto , Toshio Kobayashi , Akihiro Nakamura , Ichiro Fujiwara , Toshio Terano
IPC分类号： H01L23/48
CPC分类号： H01L27/11568 , H01L21/2815 , H01L27/115 , H01L29/6656
摘要： A semiconductor device enabling word lines to be arranged at close intervals, comprising a plurality of memory transistors arranged in an array and a plurality of word lines serving also as gate electrodes of memory transistors in a same row, extending in a row direction, and repeating in a column direction, where insulating films are formed between the plurality of word lines to insulate and isolate the word lines from each other and where a dimension of separation of word lines is defined by the thickness of the insulating films.
摘要翻译：一种半导体器件，其能够以近似的间隔布置字线，包括排列成阵列的多个存储晶体管，以及同时作为沿行方向延伸的同一行中的存储晶体管的栅电极的多条字线，并重复在列方向上，在多个字线之间形成绝缘膜以使字线彼此绝缘和隔离，并且字线分隔的尺寸由绝缘膜的厚度限定。

3. 发明授权

US07049180B2 Method of fabricating a memory transistor array utilizing insulated word lines as gate electrodes 失效
标题翻译：使用绝缘字线作为栅电极制造存储晶体管阵列的方法
公开(公告)号：US07049180B2
公开(公告)日：2006-05-23
申请号：US11098447
申请日：2005-04-05
申请人： Kazumasa Nomoto , Toshio Kobayashi , Akihiro Nakamura , Ichiro Fujiwara , Toshio Terano
发明人： Kazumasa Nomoto , Toshio Kobayashi , Akihiro Nakamura , Ichiro Fujiwara , Toshio Terano
IPC分类号： H01L21/48 , H01L29/76
CPC分类号： H01L27/11568 , H01L21/2815 , H01L27/115 , H01L29/6656
摘要： A semiconductor device enabling word lines to be arranged at close intervals, comprising a plurality of memory transistors arranged in an array and a plurality of word lines serving also as gate electrodes of memory transistors in a same row, extending in a row direction, and repeating in a column direction, where insulating films are formed between the plurality of word lines to insulate and isolate the word lines from each other and where a dimension of separation of word lines is defined by the thickness of the insulating films.
摘要翻译：一种半导体器件，其能够以近似的间隔布置字线，包括排列成阵列的多个存储晶体管，以及同时作为沿行方向延伸的同一行中的存储晶体管的栅电极的多条字线，并重复在列方向上，在多个字线之间形成绝缘膜以使字线彼此绝缘和隔离，并且字线分隔的尺寸由绝缘膜的厚度限定。

4. 发明申请

US20050255652A1 Semiconductor device and method of producing the same 失效
公开(公告)号：US20050255652A1
公开(公告)日：2005-11-17
申请号：US11098447
申请日：2005-04-05
申请人： Kazumasa Nomoto , Toshio Kobayashi , Akihiro Nakamura , Ichiro Fujiwara , Toshio Terano
发明人： Kazumasa Nomoto , Toshio Kobayashi , Akihiro Nakamura , Ichiro Fujiwara , Toshio Terano
IPC分类号： H01L21/28 , H01L21/8246 , H01L27/115 , H01L21/336
CPC分类号： H01L27/11568 , H01L21/2815 , H01L27/115 , H01L29/6656
摘要： A semiconductor device enabling word lines to be arranged at close intervals, comprising a plurality of memory transistors arranged in an array and a plurality of word lines serving also as gate electrodes of memory transistors in a same row, extending in a row direction, and repeating in a column direction, where insulating films are formed between the plurality of word lines to insulate and isolate the word lines from each other and where a dimension of separation of word lines is defined by the thickness of the insulating films.

5. 发明授权

US06891262B2 Semiconductor device and method of producing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06891262B2
公开(公告)日：2005-05-10
申请号：US10196636
申请日：2002-07-17
申请人： Kazumasa Nomoto , Toshio Kobayashi , Akihiro Nakamura , Ichiro Fujiwara , Toshio Terano
发明人： Kazumasa Nomoto , Toshio Kobayashi , Akihiro Nakamura , Ichiro Fujiwara , Toshio Terano
IPC分类号： H01L21/28 , H01L21/8246 , H01L27/115 , H01L23/48 , H01L23/04 , H01L23/495 , H01L29/788
CPC分类号： H01L27/11568 , H01L21/2815 , H01L27/115 , H01L29/6656
摘要： A semiconductor device enabling word lines to be arranged at close intervals, comprising a plurality of memory transistors arranged in an array and a plurality of word lines serving also as gate electrodes of memory transistors in a same row, extending in a row direction, and repeating in a column direction, where insulating films are formed between the plurality of word lines to insulate and isolate the word lines from each other and where a dimension of separation of word lines is defined by the thickness of the insulating films.
摘要翻译：一种半导体器件，其能够以近似的间隔布置字线，包括排列成阵列的多个存储晶体管，以及同时作为沿行方向延伸的同一行中的存储晶体管的栅电极的多条字线，并重复在列方向上，在多个字线之间形成绝缘膜，以使字线彼此绝缘和隔离，并且字线分隔的尺寸由绝缘膜的厚度限定。

6. 发明授权

US07012329B2 Memory transistor array utilizing insulated word lines as gate electrodes 失效
公开(公告)号：US07012329B2
公开(公告)日：2006-03-14
申请号：US11098503
申请日：2005-04-05
申请人： Kazumasa Nomoto , Toshio Kobayashi , Akihiro Nakamura , Ichiro Fujiwara , Toshio Terano
发明人： Kazumasa Nomoto , Toshio Kobayashi , Akihiro Nakamura , Ichiro Fujiwara , Toshio Terano
IPC分类号： H01L29/76
CPC分类号： H01L27/11568 , H01L21/2815 , H01L27/115 , H01L29/6656
摘要： A semiconductor device enabling word lines to be arranged at close intervals, comprising a plurality of memory transistors arranged in an array and a plurality of word lines serving also as gate electrodes of memory transistors in a same row, extending in a row direction, and repeating in a column direction, where insulating films are formed between the plurality of word lines to insulate and isolate the word lines from each other and where a dimension of separation of word lines is defined by the thickness of the insulating films.

7. 发明申请

US20050218522A1 Semiconductor device and method of producing the same 失效
公开(公告)号：US20050218522A1
公开(公告)日：2005-10-06
申请号：US11098501
申请日：2005-04-05
申请人： Kazumasa Nomoto , Toshio Kobayashi , Akihiro Nakamura , Ichiro Fujiwara , Toshio Terano
发明人： Kazumasa Nomoto , Toshio Kobayashi , Akihiro Nakamura , Ichiro Fujiwara , Toshio Terano
IPC分类号： H01L21/28 , H01L21/8246 , H01L27/115 , H01L21/8242
CPC分类号： H01L27/11568 , H01L21/2815 , H01L27/115 , H01L29/6656
摘要： A semiconductor device enabling word lines to be arranged at close intervals, comprising a plurality of memory transistors arranged in an array and a plurality of word lines serving also as gate electrodes of memory transistors in a same row, extending in a row direction, and repeating in a column direction, where insulating films are formed between the plurality of word lines to insulate and isolate the word lines from each other and where a dimension of separation of word lines is defined by the thickness of the insulating films.

8. 发明申请

US20050146015A1 Semiconductor device and method of producing the same 失效
公开(公告)号：US20050146015A1
公开(公告)日：2005-07-07
申请号：US11072505
申请日：2005-03-07
申请人： Kazumasa Nomoto , Toshio Kobayashi , Akihiro Nakamura , Ichiro Fujiwara , Toshio Terano
发明人： Kazumasa Nomoto , Toshio Kobayashi , Akihiro Nakamura , Ichiro Fujiwara , Toshio Terano
IPC分类号： H01L21/28 , H01L21/8246 , H01L27/115 , H01L29/76
CPC分类号： H01L27/11568 , H01L21/2815 , H01L27/115 , H01L29/6656
摘要： A semiconductor device enabling word lines to be arranged at close intervals, comprising a plurality of memory transistors arranged in an array and a plurality of word lines serving also as gate electrodes of memory transistors in a same row, extending in a row direction, and repeating in a column direction, where insulating films are formed between the plurality of word lines to insulate and isolate the word lines from each other and where a dimension of separation of word lines is defined by the thickness of the insulating films.

9. 发明申请

US20050189570A1 Semiconductor device and method of producing the same 失效
公开(公告)号：US20050189570A1
公开(公告)日：2005-09-01
申请号：US11098503
申请日：2005-04-05
申请人： Kazumasa Nomoto , Toshio Kobayashi , Akihiro Nakamura , Ichiro Fujiwara , Toshio Terano
发明人： Kazumasa Nomoto , Toshio Kobayashi , Akihiro Nakamura , Ichiro Fujiwara , Toshio Terano
IPC分类号： H01L21/28 , H01L21/8246 , H01L27/115 , H01L21/8242 , H01L23/02 , H01L27/10 , H01L29/73 , H01L29/74
CPC分类号： H01L27/11568 , H01L21/2815 , H01L27/115 , H01L29/6656
摘要： A semiconductor device enabling word lines to be arranged at close intervals, comprising a plurality of memory transistors arranged in an array and a plurality of word lines serving also as gate electrodes of memory transistors in a same row, extending in a row direction, and repeating in a column direction, where insulating films are formed between the plurality of word lines to insulate and isolate the word lines from each other and where a dimension of separation of word lines is defined by the thickness of the insulating films.

10. 发明授权

US06911691B2 Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US06911691B2
公开(公告)日：2005-06-28
申请号：US10343393
申请日：2002-05-31
申请人： Hideto Tomiie , Toshio Terano , Toshio Kobayashi
发明人： Hideto Tomiie , Toshio Terano , Toshio Kobayashi
IPC分类号： H01L21/8247 , G11C16/04 , H01L21/28 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L21/28282 , G11C16/0475 , H01L29/7923
摘要： To propose a new channel structure suitable for high efficiency source side injection, and provide a non-volatile semiconductor memory device and a charge injection method using the same. The non-volatile memory device includes a first conductivity type semiconductor substrate (SUB), a first conductivity type inversion layer-forming region (CH1), second conductivity type accumulation layer-forming regions (ACLa, ACL2b), second conductivity type regions (S/D1, S/D2), an insulating film (GD0) and a first conductive layer (CL) formed on the inversion layer-forming region (CH1). A charge accumulation film (GD) and a second conductive layer (WL) are stacked on an upper surface and side surface of the first conductive layer (CL), an exposure surface of the inversion layer-forming region (CH1), and an upper surface of the accumulation layer-forming regions (ACLa, ACLb) and the second conductivity type regions (S/D1, S/D2). The second conductive layer (WL) is connected to a word line and second conductivity type regions (S/D1, S/D2) are connected to bit lines (Bla, BLb).
摘要翻译：提出一种适用于高效率源侧注入的新型通道结构，并提供一种非易失性半导体存储器件及使用其的电荷注入方法。非易失性存储器件包括第一导电型半导体衬底（SUB），第一导电类型反型层形成区（CH 1），第二导电型蓄积层形成区（ACLa，ACL2b），第二导电类型在反转层形成区域（CH 1）上形成的区域（S / D 1，S / D 2），绝缘膜（GD 0）和第一导电层（CL）。电荷累积膜（GD）和第二导电层（WL）层叠在第一导电层（CL）的上表面和侧表面上，反型层形成区域（CH 1）的曝光表面和蓄积层形成区域（ACLa，ACLb）和第二导电类型区域（S / D 1，S / D 2）的上表面。第二导电层（WL）连接到字线，第二导电类型区域（S / D 1，S / D 2）连接到位线（Bla，BLb）。

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