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1. 发明授权

US08422327B2 Semiconductor device having nonvolatile memory element and manufacturing method thereof 有权
标题翻译：具有非易失性存储元件的半导体器件及其制造方法
公开(公告)号：US08422327B2
公开(公告)日：2013-04-16
申请号：US12801124
申请日：2010-05-24
申请人： Kazuhiro Teramoto , Hiroki Fujisawa , Susumu Takahashi
发明人： Kazuhiro Teramoto , Hiroki Fujisawa , Susumu Takahashi
IPC分类号： G11C17/18
CPC分类号： G11C29/02 , G11C17/165 , G11C29/027 , G11C29/785 , G11C29/846
摘要： To provide a semiconductor device including a pair of antifuse elements at either a high level or a low level, an OR circuit that outputs different logic information for a case that at least one of the antifuse elements is at a high level and a case that both of the antifuse elements are at a low level, and an exclusive OR circuit that outputs different logic information for a case that the logic states are different from each other and a case that they are same as each other.
摘要翻译：为了提供一种包括高电平或低电平的一对反熔丝元件的半导体器件，OR电路为至少一个反熔丝元件处于高电平的情况下输出不同的逻辑信息，以及两个的反熔丝元件为低电平，异或电路输出逻辑状态彼此不同的情况下的不同的逻辑信息以及彼此相同的情况。

2. 发明申请

US20100302833A1 Semiconductor device having nonvolatile memory element and manufacturing method thereof 有权
标题翻译：具有非易失性存储元件的半导体器件及其制造方法
公开(公告)号：US20100302833A1
公开(公告)日：2010-12-02
申请号：US12801124
申请日：2010-05-24
申请人： Kazuhiro Teramoto , Hiroki Fujisawa , Susumu Takahashi
发明人： Kazuhiro Teramoto , Hiroki Fujisawa , Susumu Takahashi
IPC分类号： G11C17/00 , G11C29/04
CPC分类号： G11C29/02 , G11C17/165 , G11C29/027 , G11C29/785 , G11C29/846
摘要： To provide a semiconductor device including a pair of antifuse elements at either a high level or a low level, an OR circuit that outputs different logic information for a case that at least one of the antifuse elements is at a high level and a case that both of the antifuse elements are at a low level, and an exclusive OR circuit that outputs different logic information for a case that the logic states are different from each other and a case that they are same as each other.
摘要翻译：为了提供一种包括高电平或低电平的一对反熔丝元件的半导体器件，OR电路为至少一个反熔丝元件处于高电平的情况下输出不同的逻辑信息，以及两个的反熔丝元件为低电平，异或电路输出逻辑状态彼此不同的情况下的不同的逻辑信息以及彼此相同的情况。

3. 发明申请

US20090016139A1 SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：半导体存储设备
公开(公告)号：US20090016139A1
公开(公告)日：2009-01-15
申请号：US12169873
申请日：2008-07-09
申请人： Kazuhiro Teramoto , Yoji Idei , Takenori Sato , Hiroki Fujisawa
发明人： Kazuhiro Teramoto , Yoji Idei , Takenori Sato , Hiroki Fujisawa
IPC分类号： G11C5/14
CPC分类号： G11C5/14 , G11C7/08 , G11C11/4091
摘要： A semiconductor storage device is provided which enables use of an overdrive method at low voltage and for a small device area. The semiconductor device includes: memory cells; sense amplifiers, each having P-channel and N-channel MOS transistors and amplifying a signal read from a memory cell; a first power supply line connected to a source terminal of the P-channel MOS transistor provided in each of the sense amplifiers; a second power supply line which supplies an overdrive voltage to the sense amplifiers at a potential higher than a write potential of the memory cell; a third power supply line connected to an external power supply, a connection element which connects and disconnects the first power supply line and the second power supply line; a capacitance element connected to the second power supply line; and a resistance element inserted between the second power supply line and the third power supply line.
摘要翻译：提供一种半导体存储装置，其能够在低电压和小的装置区域中使用过驱动方法。半导体器件包括：存储单元; 读出放大器，每个具有P沟道和N沟道MOS晶体管，并放大从存储单元读取的信号; 连接到设置在每个读出放大器中的P沟道MOS晶体管的源极端子的第一电源线; 第二电源线，其以比存储单元的写入电位高的电位向读出放大器提供过驱动电压; 连接到外部电源的第三电源线，连接和断开第一电源线和第二电源线的连接元件; 连接到第二电源线的电容元件; 以及插入在第二电源线和第三电源线之间的电阻元件。

4. 发明授权

US07719911B2 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US07719911B2
公开(公告)日：2010-05-18
申请号：US12169873
申请日：2008-07-09
申请人： Kazuhiro Teramoto , Yoji Idei , Takenori Sato , Hiroki Fujisawa
发明人： Kazuhiro Teramoto , Yoji Idei , Takenori Sato , Hiroki Fujisawa
IPC分类号： G11C7/00
CPC分类号： G11C5/14 , G11C7/08 , G11C11/4091
摘要： A semiconductor storage device is provided which enables use of an overdrive method at low voltage and for a small device area. The semiconductor device includes: memory cells; sense amplifiers, each having P-channel and N-channel MOS transistors and amplifying a signal read from a memory cell; a first power supply line connected to a source terminal of the P-channel MOS transistor provided in each of the sense amplifiers; a second power supply line which supplies an overdrive voltage to the sense amplifiers at a potential higher than a write potential of the memory cell; a third power supply line connected to an external power supply, a connection element which connects and disconnects the first power supply line and the second power supply line; a capacitance element connected to the second power supply line; and a resistance element inserted between the second power supply line and the third power supply line.
摘要翻译：提供一种半导体存储装置，其能够在低电压和小的装置区域中使用过驱动方法。半导体器件包括：存储单元; 读出放大器，每个具有P沟道和N沟道MOS晶体管，并放大从存储单元读取的信号; 连接到设置在每个读出放大器中的P沟道MOS晶体管的源极端子的第一电源线; 第二电源线，其以比存储单元的写入电位高的电位向读出放大器提供过驱动电压; 连接到外部电源的第三电源线，连接和断开第一电源线和第二电源线的连接元件; 连接到第二电源线的电容元件; 以及插入在第二电源线和第三电源线之间的电阻元件。

5. 发明授权

US07675347B2 Semiconductor device operating in an active mode and a standby mode 失效
标题翻译：半导体器件工作在主动模式和待机模式
公开(公告)号：US07675347B2
公开(公告)日：2010-03-09
申请号：US11984464
申请日：2007-11-19
申请人： Kazuhiro Teramoto , Yoji Idei
发明人： Kazuhiro Teramoto , Yoji Idei
IPC分类号： H03K3/01
CPC分类号： H03K3/356113 , H03K19/0016 , H03K2217/0018
摘要： A semiconductor device operates in an active mode or a standby mode, and includes a substrate-potential power source line supplying a substrate potential which is higher in a standby mode than in an active mode, and a source-potential power source line supplying a source potential which is lower in a standby mode than in an active mode. During a mode shift from the standby mode to the active mode, a potential equalizing transistor is turned ON to pass a current flowing from the substrate-potential power source line to the source-potential power source line, to reduce the time length needed for shifting from the standby mode to the active mode.
摘要翻译：半导体器件以活动模式或待机模式工作，并且包括提供在待机模式下比在活动模式中更高的衬底电位的衬底电位电源线以及提供源的源极 - 电位电源线待机模式下的电位低于活动模式。在从待机模式切换到激活模式的模式期间，电位均衡晶体管导通以使从衬底电位电源线流到源极电源线的电流通过，以减少移位所需的时间长度从待机模式到活动模式。

6. 发明申请

US20090016126A1 SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：半导体存储器件
公开(公告)号：US20090016126A1
公开(公告)日：2009-01-15
申请号：US12170561
申请日：2008-07-10
申请人： Kazuhiro Teramoto , Yoji Idei , Takenori Sato
发明人： Kazuhiro Teramoto , Yoji Idei , Takenori Sato
IPC分类号： G11C7/00 , G11C8/08
CPC分类号： G11C29/02 , G11C29/025 , G11C29/50008 , G11C2029/1204 , G11C2029/5006
摘要： A semiconductor memory device is provided that is capable of detecting a short circuit defect to be detected in a memory array without causing an error due to off-current of a sense amplifier circuit. Sense amplifier circuits amplify a potential between a pair of bit lines, which occurs based on potential of memory cells selected by driving word lines and bit lines. Selection transistors are provided between the bit lines and the sense amplifier circuits. A word-SE interval control circuit included in an X timing generating circuit turns off the selection transistors and disconnects the bit lines from the sense amplifier circuits based on a signal representing a test state for expanded time when a test to expand an interval between word line driving and activation of the sense amplifier circuits and detect defect sites of the bit lines is performed.
摘要翻译：提供一种半导体存储器件，其能够检测在存储器阵列中要检测的短路缺陷，而不会由于读出放大器电路的截止电流而引起误差。感测放大器电路根据通过驱动字线和位线选择的存储器单元的电位放大一对位线之间的电位。选择晶体管设置在位线和读出放大器电路之间。包括在X定时发生电路中的字SE间隔控制电路关闭选择晶体管，并且当扩展字线之间的间隔的测试时，基于表示用于扩展时间的测试状态的信号，从读出放大器电路断开位线执行感测放大器电路的驱动和激活并检测位线的缺陷位置。

7. 发明授权

US08331165B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08331165B2
公开(公告)日：2012-12-11
申请号：US12909016
申请日：2010-10-21
申请人： Kazuhiro Teramoto
发明人： Kazuhiro Teramoto
IPC分类号： G11C5/14
CPC分类号： G11C11/4093 , G11C7/02 , G11C7/1066 , G11C7/222 , G11C11/4076
摘要： A semiconductor device includes a plurality of first output terminals 1-13 and a plurality of first output circuits 203,204 provided corresponding to each of the plurality of first output terminals and coupled to a corresponding first output terminal. The semiconductor device further includes a second output circuit 201 coupled to a second output terminal DQS. The second output circuit automatically adjusts a slew rate based on the state transitions of the plurality of first output circuits. The second output circuit adjusts the slew rate from a first state to a second state based on a transition from first data outputted from the first output circuit to second data following said first data. The second output circuit outputs data in synchronization with the second data with a slew rate in said second state.
摘要翻译：半导体器件包括多个第一输出端子1-13和与多个第一输出端子中的每一个相对应地设置并耦合到相应的第一输出端子的多个第一输出电路203,204。半导体器件还包括耦合到第二输出端子DQS的第二输出电路201。第二输出电路基于多个第一输出电路的状态转换自动调整转换速率。第二输出电路基于从第一输出电路输出的第一数据到所述第一数据之后的第二数据的转变，将转换速率从第一状态调整到第二状态。第二输出电路在第二状态下以转换速率与第二数据同步地输出数据。

8. 发明申请

US20110096613A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110096613A1
公开(公告)日：2011-04-28
申请号：US12909016
申请日：2010-10-21
申请人： Kazuhiro Teramoto
发明人： Kazuhiro Teramoto
IPC分类号： G11C7/22 , H03K19/003
CPC分类号： G11C11/4093 , G11C7/02 , G11C7/1066 , G11C7/222 , G11C11/4076
摘要： A semiconductor device includes a plurality of first output terminals 1-13 and a plurality of first output circuits 203,204 provided corresponding to each of the plurality of first output terminals and coupled to a corresponding first output terminal. The semiconductor device further includes a second output circuit 201 coupled to a second output terminal DQS. The second output circuit automatically adjusts a slew rate based on the state transitions of the plurality of first output circuits. The second output circuit adjusts the slew rate from a first state to a second state based on a transition from first data outputted from the first output circuit to second data following said first data. The second output circuit outputs data in synchronization with the second data with a slew rate in said second state.
摘要翻译：半导体器件包括多个第一输出端子1-13和与多个第一输出端子中的每一个相对应地设置并耦合到相应的第一输出端子的多个第一输出电路203,204。半导体器件还包括耦合到第二输出端子DQS的第二输出电路201。第二输出电路基于多个第一输出电路的状态转换自动调整转换速率。第二输出电路基于从第一输出电路输出的第一数据到所述第一数据之后的第二数据的转变，将转换速率从第一状态调整到第二状态。第二输出电路在第二状态下以转换速率与第二数据同步地输出数据。

9. 发明授权

US07649790B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07649790B2
公开(公告)日：2010-01-19
申请号：US12170561
申请日：2008-07-10
申请人： Kazuhiro Teramoto , Yoji Idei , Takenori Sato
发明人： Kazuhiro Teramoto , Yoji Idei , Takenori Sato
IPC分类号： G11C29/00
CPC分类号： G11C29/02 , G11C29/025 , G11C29/50008 , G11C2029/1204 , G11C2029/5006
摘要： A semiconductor memory device is provided that is capable of detecting a short circuit defect to be detected in a memory array without causing an error due to off-current of a sense amplifier circuit. Sense amplifier circuits amplify a potential between a pair of bit lines, which occurs based on potential of memory cells selected by driving word lines and bit lines. Selection transistors are provided between the bit lines and the sense amplifier circuits. A word-SE interval control circuit included in an X timing generating circuit turns off the selection transistors and disconnects the bit lines from the sense amplifier circuits based on a signal representing a test state for expanded time when a test to expand an interval between word line driving and activation of the sense amplifier circuits and detect defect sites of the bit lines is performed.
摘要翻译：提供一种半导体存储器件，其能够检测在存储器阵列中要检测的短路缺陷，而不会由于读出放大器电路的截止电流而引起误差。感测放大器电路根据通过驱动字线和位线选择的存储器单元的电位放大一对位线之间的电位。选择晶体管设置在位线和读出放大器电路之间。包括在X定时发生电路中的字SE间隔控制电路关闭选择晶体管，并且当扩展字线之间的间隔的测试时，基于表示用于扩展时间的测试状态的信号，从读出放大器电路断开位线执行感测放大器电路的驱动和激活并检测位线的缺陷位置。

10. 发明授权

US08325550B2 Semiconductor memory device and method of controlling auto-refresh 有权
标题翻译：半导体存储器件和控制自动刷新的方法
公开(公告)号：US08325550B2
公开(公告)日：2012-12-04
申请号：US12656178
申请日：2010-01-20
申请人： Kazuhiro Teramoto
发明人： Kazuhiro Teramoto
IPC分类号： G11C7/00 , G11C7/04
CPC分类号： G11C7/04 , G11C11/406 , G11C11/40611 , G11C11/40626 , G11C2211/4061
摘要： Auto-refresh of a semiconductor device may be controlled by setting the number of auto-refresh to be performed in a period of time, based on temperature, when an auto-refresh command is detected.
摘要翻译：可以通过在检测到自动刷新命令时基于温度来设定要在一段时间内执行的自动刷新次数来控制半导体器件的自动刷新。

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