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1. 发明授权

US08742786B2 Semiconductor device and operation monitoring method for semiconductor device 有权
标题翻译：半导体器件的半导体器件和操作监控方法
公开(公告)号：US08742786B2
公开(公告)日：2014-06-03
申请号：US12410157
申请日：2009-03-24
申请人： Kazufumi Komura , Katsumi Furukawa , Keiichi Fujimura , Takayoshi Nakamura , Tohru Yasuda , Hirohisa Nishiyama , Nobuyoshi Nakaya , Kanta Yamamoto , Shigetaka Asano
发明人： Kazufumi Komura , Katsumi Furukawa , Keiichi Fujimura , Takayoshi Nakamura , Tohru Yasuda , Hirohisa Nishiyama , Nobuyoshi Nakaya , Kanta Yamamoto , Shigetaka Asano
IPC分类号： G01R31/02
CPC分类号： G01R31/318555 , G01R31/318533 , G01R31/318552
摘要： A semiconductor device includes a monitor including a first element coupled between a first power supply line and a second power supply line, and a load for increasing a load value between the first element and the first power supply line or the second power supply line, and a determination unit which determines an operating state of the first element based on an output of the monitor.
摘要翻译：一种半导体器件包括：监测器，包括耦合在第一电源线和第二电源线之间的第一元件和用于增加第一元件与第一电源线或第二电源线之间的负载值的负载;以及确定单元，其基于所述监视器的输出来确定所述第一元素的操作状态。

2. 发明申请

US20060220722A1 Power consumption reduction circuit for clock network 有权
标题翻译：时钟网络功耗降低电路
公开(公告)号：US20060220722A1
公开(公告)日：2006-10-05
申请号：US11220676
申请日：2005-09-08
申请人： Kazufumi Komura , Takayoshi Nakamura , Keiichi Fujimura , Masahito Hirose , Keigo Nakashima , Masaki Nagato
发明人： Kazufumi Komura , Takayoshi Nakamura , Keiichi Fujimura , Masahito Hirose , Keigo Nakashima , Masaki Nagato
IPC分类号： G06F1/04
CPC分类号： G06F1/32 , G06F1/10 , G06F1/3237 , G06F1/3287 , Y02D10/128 , Y02D10/171
摘要： A power consumption reduction circuit for reducing power consumed by a clock tree network including a transmission control circuit. The power consumption reduction circuit includes a transmission control circuit for controlling transmission of the clock signal to the buffer circuit group so as to selectively provide and interrupt the clock signal. A switch circuit disconnects the buffer circuit group from a power supply when the transmission control circuit interrupts the clock signal.
摘要翻译：一种用于减少由包括传输控制电路的时钟树网络消耗的功率的功耗降低电路。功耗降低电路包括用于控制时钟信号传输到缓冲电路组的传输控制电路，以选择性地提供和中断时钟信号。当传输控制电路中断时钟信号时，开关电路将缓冲电路组与电源断开。

3. 发明申请

US20070195946A1 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US20070195946A1
公开(公告)日：2007-08-23
申请号：US11442152
申请日：2006-05-30
申请人： Kazufumi Komura , Takayoshi Nakamura , Keiichi Fujimura , Masahito Hirose , Keigo Nakashima , Masaki Nagato
发明人： Kazufumi Komura , Takayoshi Nakamura , Keiichi Fujimura , Masahito Hirose , Keigo Nakashima , Masaki Nagato
IPC分类号： H04M3/00
CPC分类号： H01L23/5223 , H01L23/5286 , H01L2924/0002 , Y10S257/908 , H01L2924/00
摘要： A semiconductor integrated circuit device provided with a plurality of power supply wire layers including a first potential power supply wire and a second potential power supply wire formed in different layers. At least one capacitor contact wire extends from one of the first and second potential power supply wires toward the other one of the first and second potential power supply wires so as to form a capacitor between each capacitor contact wire and its surrounding wires.
摘要翻译：一种半导体集成电路装置，具备包括形成在不同层中的第一潜在电源线和第二潜在电源线的多个电源线层。至少一个电容器接触线从第一和第二电势电源线中的一个延伸到第一和第二电势电源线中的另一个，以便在每个电容器接触线和其周围的线之间形成电容器。

4. 发明授权

US07663175B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US07663175B2
公开(公告)日：2010-02-16
申请号：US11442152
申请日：2006-05-30
申请人： Kazufumi Komura , Takayoshi Nakamura , Keiichi Fujimura , Masahito Hirose , Keigo Nakashima , Masaki Nagato
发明人： Kazufumi Komura , Takayoshi Nakamura , Keiichi Fujimura , Masahito Hirose , Keigo Nakashima , Masaki Nagato
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L23/5223 , H01L23/5286 , H01L2924/0002 , Y10S257/908 , H01L2924/00
摘要： A semiconductor integrated circuit device provided with a plurality of power supply wire layers including a first potential power supply wire and a second potential power supply wire formed in different layers. At least one capacitor contact wire extends from one of the first and second potential power supply wires toward the other one of the first and second potential power supply wires so as to form a capacitor between each capacitor contact wire and its surrounding wires.
摘要翻译：一种半导体集成电路装置，具备包括形成在不同层中的第一潜在电源线和第二潜在电源线的多个电源线层。至少一个电容器接触线从第一和第二电势电源线中的一个延伸到第一和第二电势电源线中的另一个，以便在每个电容器接触导线及其周围电线之间形成电容器。

5. 发明授权

US07463076B2 Power consumption reduction circuit for clock network 有权
标题翻译：时钟网络功耗降低电路
公开(公告)号：US07463076B2
公开(公告)日：2008-12-09
申请号：US11220676
申请日：2005-09-08
申请人： Kazufumi Komura , Takayoshi Nakamura , Keiichi Fujimura , Masahito Hirose , Keigo Nakashima , Masaki Nagato
发明人： Kazufumi Komura , Takayoshi Nakamura , Keiichi Fujimura , Masahito Hirose , Keigo Nakashima , Masaki Nagato
IPC分类号： G06F1/04
CPC分类号： G06F1/32 , G06F1/10 , G06F1/3237 , G06F1/3287 , Y02D10/128 , Y02D10/171
摘要： A power consumption reduction circuit for reducing power consumed by a clock tree network including a transmission control circuit. The power consumption reduction circuit includes a transmission control circuit for controlling transmission of the clock signal to the buffer circuit group so as to selectively provide and interrupt the clock signal. A switch circuit disconnects the buffer circuit group from a power supply when the transmission control circuit interrupts the clock signal.
摘要翻译：一种用于降低由包括传输控制电路的时钟树网络消耗的功率的功耗降低电路。功耗降低电路包括用于控制时钟信号传输到缓冲电路组的传输控制电路，以选择性地提供和中断时钟信号。当传输控制电路中断时钟信号时，开关电路将缓冲电路组与电源断开。

6. 发明授权

US08023353B2 Semiconductor memory device, refresh control method thereof, and test method thereof 有权
标题翻译：半导体存储器件，其刷新控制方法及其测试方法
公开(公告)号：US08023353B2
公开(公告)日：2011-09-20
申请号：US12818956
申请日：2010-06-18
申请人： Masami Nakashima , Yoshiharu Kato , Kazufumi Komura
发明人： Masami Nakashima , Yoshiharu Kato , Kazufumi Komura
IPC分类号： G11C7/00
CPC分类号： G11C29/50016 , G11C8/18 , G11C11/401 , G11C11/406 , G11C11/40603 , G11C29/028 , G11C29/50 , G11C29/783 , G11C2207/2227 , G11C2211/4061 , G11C2211/4067
摘要： The present invention provides a semiconductor memory device which reduces current consumption in a standby state owing to a suitable refresh-thinning-out function, and a refresh control method thereof. When the refresh-thinning-out function is added while a refresh operation and an external access operation are being executed independently of each other, a refresh address counter outputs a refresh address Add(C) and inputs predetermined high-order bits thereof to a refresh-thinning-out control as a high-order refresh address Add(C) (m), where judgment as to whether the refresh operation is performed, is made. A refresh permission signal RFEN corresponding to the result of judgment is inputted to a word driver to activate and control the word driver. The process of judgment by the refresh-thinning-out control circuit can be embedded in an access time of a row system.
摘要翻译：本发明提供一种由于适当的刷新稀疏功能而在待机状态下减少电流消耗的半导体存储器件及其刷新控制方法。当刷新操作和外部访问操作彼此独立地执行时添加刷新稀疏功能时，刷新地址计数器输出刷新地址Add（C）并将预定的高位比特输入到刷新 - 作为高阶刷新地址的输出控制Add（C）（m），其中进行关于刷新操作的判断。与判断结果相对应的刷新允许信号RFEN被输入到字驱动器以激活和控制字驱动器。刷新稀疏控制电路的判断处理可嵌入行系统的访问时间。

7. 发明申请

US20070237014A1 Semiconductor memory device and method of controlling the semiconductor memory device 失效
标题翻译：半导体存储器件和控制半导体存储器件的方法
公开(公告)号：US20070237014A1
公开(公告)日：2007-10-11
申请号：US11806721
申请日：2007-06-04
申请人： Kazufumi Komura , Yoshiharu Kato , Satoru Kawamoto
发明人： Kazufumi Komura , Yoshiharu Kato , Satoru Kawamoto
IPC分类号： G11C7/00
CPC分类号： G11C11/4094 , G11C11/4076 , G11C2207/005
摘要： It is an object to provide a semiconductor memory device that can conduct the equalizing operation of bit lines with a low current consumption while maintaining a normal accessing speed and the chip area, and a control method thereof. In a semiconductor memory device of the shared sense amplification system, in a predetermined number of times which is (k−1) times or less among k-times of continuous word line selections of a selected memory block, the bit line separation gate of the unselected memory block is rendered conductive in the active period of the equalizing unit after the word line selection. Also, a circuit that equalizes a wiring higher in the capacity component is driven by a higher voltage level according to the wiring capacity component of the sense amplification power supply line and the bit lines, to thereby equalize the power supply line and the bit line in the equal time, thereby being capable of preventing the short-circuiting within the sense amplifier.
摘要翻译：本发明的目的是提供一种半导体存储器件及其控制方法，该半导体存储器件可以在保持正常访问速度和芯片面积的同时以低电流消耗进行位线的均衡操作。在共享读出放大系统的半导体存储器件中，在所选择的存储器块的连续字线选择的k次之间的预定次数（k-1）倍以下的情况下，位线分离门未选择的存储块在字线选择之后的均衡单元的有效周期内变为导通。此外，根据感测放大电源线和位线的布线电容分量，通过较高的电压电平驱动均衡电容分量较高的布线的电路，从而使电源线和位线的均匀化相等的时间，从而能够防止读出放大器内的短路。

8. 发明授权

US06490215B2 Semiconductor memory device and refreshing method of semiconductor memory device 有权
标题翻译：半导体存储器件和半导体存储器件的刷新方法
公开(公告)号：US06490215B2
公开(公告)日：2002-12-03
申请号：US09861545
申请日：2001-05-22
申请人： Kazufumi Komura , Takaaki Furuyama , Satoru Kawamoto
发明人： Kazufumi Komura , Takaaki Furuyama , Satoru Kawamoto
IPC分类号： G11C700
CPC分类号： G11C11/406
摘要： A semiconductor memory device that suppresses an increase in the circuit area which is originated from the layout of address signal lines. The semiconductor memory device includes refresh address counters, a switch circuit, and address holding circuits. The refresh address counters generate refresh address signals associated with banks in response to a refresh request signal. The switch circuit selectively outputs the external address signal and a refresh address signal generated by one of the refresh address counters in accordance with the refresh request signal. Each of the address holding circuits holds the refresh address signal or the external address signal output from the switch circuit and supplies the held address signal to an associated one of the banks.
摘要翻译：一种半导体存储器件，其抑制来自地址信号线的布局的电路面积的增加。半导体存储器件包括刷新地址计数器，开关电路和地址保持电路。刷新地址计数器响应于刷新请求信号产生与存储体相关联的刷新地址信号。开关电路根据刷新请求信号有选择地输出外部地址信号和由刷新地址计数器之一产生的刷新地址信号。每个地址保持电路保持从开关电路输出的刷新地址信号或外部地址信号，并将保持的地址信号提供给相关的一个存储体。

9. 发明授权

US07872293B2 Capacitance cell, semiconductor device, and capacitance cell arranging method 有权
标题翻译：电容电池，半导体器件和电容电池配置方法
公开(公告)号：US07872293B2
公开(公告)日：2011-01-18
申请号：US11482012
申请日：2006-07-07
申请人： Kazufumi Komura
发明人： Kazufumi Komura
IPC分类号： H01L29/94
CPC分类号： H01L23/5223 , H01L28/87 , H01L2924/0002 , H01L2924/00
摘要： A capacitance cell 21 is wired while using adjacent wiring layers Ma and Mb as a pair of electrode layers T1 and T2 orthogonally to opposed lateral end faces out of lateral end faces X1, X2, Y1, and Y2 that section the cell in a plane direction. Contact surfaces of electrode surfaces T1 and T2 with the lateral end faces are second connection terminals T12 and T22. For longitudinal pathways, first and second via contact layers V1 and V2are connected. The first via contact layer V1 interconnects the wiring layers Ma and Mb. The second via contact layer V2 is connected to a wiring layer located outside beyond an upper or lower end face Z2, Z1. The second via contact layer V2 is connected to a first connection terminal T11, T21 located on the upper or lower end faces Z2, Z1. The capacitance cells 21 are linked via the first and second connection terminals so that a capacitance element having a free shape is formed. A capacitance cell, a semiconductor device, and a capacitance element arranging method that allow to arrange capacitance elements each using wiring layers sandwiching an interlayer insulating film with less of a leak current as electrode layers according to the shapes of unused areas.
摘要翻译：在使用相邻布线层Ma和Mb作为一对电极层T1和T2的正面相对的侧面端面X1，X2，Y1和Y2之间的电容单元21被布线，该横向端面X1，X2，Y1和Y2在平面方向上分割单元。具有侧端面的电极表面T1和T2的接触表面是第二连接端子T12和T22。对于纵向路径，第一和第二通孔接触层V1和V2连接。第一通孔接触层V1互连布线层Ma和Mb。第二通孔接触层V2连接到位于外侧或上端面Z2，Z1外侧的布线层。第二通孔接触层V2连接到位于上端面或下端面Z2，Z1上的第一连接端子T11，T21。电容单元21通过第一和第二连接端子连接，从而形成具有自由形状的电容元件。电容单元，半导体器件和电容元件配置方法，其能够根据未使用区域的形状，使用夹着具有较小漏电流的层间绝缘膜的布线层来布置电容元件作为电极层。

10. 发明申请

US20070079198A1 Semiconductor integrated circuit apparatus and interface test method 失效
标题翻译：半导体集成电路设备及接口测试方法
公开(公告)号：US20070079198A1
公开(公告)日：2007-04-05
申请号：US11319515
申请日：2005-12-29
申请人： Kazufumi Komura
发明人： Kazufumi Komura
IPC分类号： G01R31/28
CPC分类号： G01R31/31905 , G01R31/31716 , G01R31/31926 , G11C29/02 , G11C29/022 , G11C29/50012 , G11C29/56 , G11C2029/5602
摘要： An interface test can be performed by, for example, only a self apparatus when interface operation specifications are different between the self apparatus and an original connection partner apparatus. An LSI has a plurality of interfaces (IFs) for transmission/reception of data with an external device, and the LSI includes an emulation control unit for allowing one of the two of the plurality of IFs to perform an operation of emulating an IF of a connection partner device having operation specifications different from those of the LSI, when two Ifs are connected each other via a transmission line.
摘要翻译：当接口操作规范在自身设备和原始连接伙伴设备之间是不同的时，接口测试例如可以仅由自身设备执行。 LSI具有用于与外部设备发送/接收数据的多个接口（IF），并且LSI包括用于允许多个IF中的两个IF之一执行仿真IF的IF的操作的仿真控制单元具有不同于LSI的操作规范的连接伙伴装置，当两个If通过传输线相互连接时。

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