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    • 1. 发明授权
    • Synchronous semiconductor memory
    • 同步半导体存储器
    • US06826104B2
    • 2004-11-30
    • US10227779
    • 2002-08-26
    • Kazuaki KawaguchiShigeo Ohshima
    • Kazuaki KawaguchiShigeo Ohshima
    • G11C700
    • G11C11/406G11C11/4076
    • In an FCRAM having a late write function, when a first command signal indicates “write active”, whether a write operation or an auto-refresh operation is to be performed is determined on the basis of a second command signal. For example, when the second command signal indicates “write”, a write operation for a memory cell is performed by a late write scheme. When the second command signal indicates “auto-refresh”, an auto-refresh operation is performed. In the last write cycle of a write operation immediately preceding this auto-refresh operation, addresses for selecting a memory cell as an object of auto-refresh are predetermined. After data write to a memory cell is completed in the last write cycle, row precharge for auto-refresh is performed. After that, an auto-refresh operation (i.e., a data read operation and a data restore operation) is performed for the selected memory cell.
    • 在具有迟写功能的FCRAM中,当第一命令信号指示“写活动”时,是否要执行写操作或自动刷新操作是基于第二命令信号确定的。 例如,当第二命令信号指示“写入”时,通过后期写入方案执行存储器单元的写入操作。 当第二命令信号指示“自动刷新”时,执行自动刷新操作。 在紧接在该自动刷新操作之前的写入操作的最后写入周期中,预定用于选择作为自动刷新对象的存储单元的地址。 在最后一个写入周期内对存储单元的数据写入完成后,执行自动刷新的行预充电。 之后,对所选择的存储单元执行自动刷新操作(即,数据读取操作和数据恢复操作)。
    • 2. 发明申请
    • Synchronous semiconductor memory
    • 同步半导体存储器
    • US20050036378A1
    • 2005-02-17
    • US10948818
    • 2004-09-23
    • Kazuaki KawaguchiShigeo Ohshima
    • Kazuaki KawaguchiShigeo Ohshima
    • G11C11/406G11C11/4076G11C7/00
    • G11C11/406G11C11/4076
    • In an FCRAM having a late write function, when a first command signal indicates “write active”, whether a write operation or an auto-refresh operation is to be performed is determined on the basis of a second command signal. For example, when the second command signal indicates “write”, a write operation for a memory cell is performed by a late write scheme. When the second command signal indicates “auto-refresh”, an auto-refresh operation is performed. In the last write cycle of a write operation immediately preceding this auto-refresh operation, addresses for selecting a memory cell as an object of auto-refresh are predetermined. After data write to a memory cell is completed in the last write cycle, row precharge for auto-refresh is performed. After that, an auto-refresh operation (i.e., a data read operation and a data restore operation) is performed for the selected memory cell.
    • 在具有迟写功能的FCRAM中,当第一命令信号指示“写活动”时,是否要执行写操作或自动刷新操作是基于第二命令信号确定的。 例如,当第二命令信号指示“写入”时,通过后期写入方案执行存储器单元的写入操作。 当第二命令信号指示“自动刷新”时,执行自动刷新操作。 在紧接在该自动刷新操作之前的写入操作的最后写入周期中,预定用于选择作为自动刷新对象的存储单元的地址。 在最后一个写入周期内对存储单元的数据写入完成后,执行自动刷新的行预充电。 之后,对所选择的存储单元执行自动刷新操作(即,数据读取操作和数据恢复操作)。
    • 5. 发明授权
    • Synchronous semiconductor memory device having dynamic memory cells and operating method thereof
    • 具有动态存储单元的同步半导体存储器件及其操作方法
    • US06879540B2
    • 2005-04-12
    • US10370416
    • 2003-02-19
    • Keiji MaruyamaShigeo OhshimaKazuaki Kawaguchi
    • Keiji MaruyamaShigeo OhshimaKazuaki Kawaguchi
    • G11C11/34G11C11/403G11C11/406G11C11/407G11C8/00
    • G11C11/40603G11C11/406G11C11/40611G11C2211/4061
    • A synchronous semiconductor memory device includes a memory cell array and a command decoder. In the memory cell array, dynamic memory cells are arranged in a matrix form. The command decoder decodes a plurality of commands in synchronism with an external clock signal. The plurality of commands are set by combinations of logical levels of a plurality of control pins at input timing of a first command and at input timing of a second command one cycle after the input timing of the first command. The command decoder includes a first decode section which determines a read operation, a second decode section which determines a write operation, and a third decode section which determines an auto-refresh operation. Setting of an auto-refresh command is determined only by a combination of the logical levels of the plurality of control pins at the input timing of the first command.
    • 同步半导体存储器件包括存储单元阵列和命令解码器。 在存储单元阵列中,动态存储单元以矩阵形式排列。 命令解码器与外部时钟信号同步地解码多个命令。 多个命令通过多个控制引脚的逻辑电平的组合在第一命令的输入定时和在第一命令的输入定时之后的一个周期的第二命令的输入定时来设置。 命令解码器包括确定读取操作的第一解码部分,确定写入操作的第二解码部分和确定自动刷新操作的第三解码部分。 仅通过在第一命令的输入定时处的多个控制引脚的逻辑电平的组合来确定自动刷新命令的设置。
    • 7. 发明授权
    • Synchronous semiconductor memory device
    • 同步半导体存储器件
    • US06731559B2
    • 2004-05-04
    • US10244962
    • 2002-09-17
    • Kazuaki KawaguchiShigeo Ohshima
    • Kazuaki KawaguchiShigeo Ohshima
    • G11C700
    • G11C7/04G11C7/1066G11C7/1072
    • A synchronous semiconductor memory device has a memory section which includes a memory cell array having a plurality of memory cells and which is capable of a read operation of reading information from the memory cells according to a read command and a write operation of writing information into the memory cells according to a write command. The synchronous semiconductor memory device further has a command sensing circuit which senses whether a first command inputted in synchronization with an external clock signal is the read command or the write command. The synchronous semiconductor memory device further has a bank timer circuit which, when the command sensing circuit has sensed either the read command or the write command, sets the end time of the restore operation of a row address strobe (RAS) and the start time of the precharge operation of the RAS according to the external clock signal.
    • 同步半导体存储器件具有存储器部分,其包括具有多个存储器单元的存储器单元阵列,并且能够根据读取命令和将信息写入到存储器单元的读取操作从存储器单元读取信息的读取操作 内存单元根据写命令。 同步半导体存储器件还具有命令检测电路,其检测与外部时钟信号同步输入的第一命令是读命令还是写指令。 同步半导体存储器件还具有一个存储体定时器电路,当命令​​感测电路感测到读取命令或写入命令时,设置行地址选通(RAS)的恢复操作的结束时间和开始时间 RAS的预充电操作根据外部时钟信号。
    • 10. 发明授权
    • Test device and test method for resistive random access memory and resistive random access memory device
    • 电阻随机存取存储器和电阻随机存取存储器件的测试装置和测试方法
    • US08593852B2
    • 2013-11-26
    • US13238479
    • 2011-09-21
    • Kazuaki KawaguchiKazushige Kanda
    • Kazuaki KawaguchiKazushige Kanda
    • G11C11/00
    • G11C29/56G11C11/16G11C13/00G11C29/50012G11C29/56012
    • According to the embodiments, a first write enable signal that changes with a constant period and a second write enable signal that changes at a time portion in which a limit time between activation/deactivation control of word lines and activation/deactivation control of bit lines is checked are input, a plurality of core control signals in which a time interval with which the core control signals change is locally shorter than a period of the first write enable signal based on the first write enable signal and the second write enable signal that are input is generated, and an operation verification of the resistive random access memory is performed by using the generated core control signals, whereby a cycle time in an arbitrary test cycle is locally and arbitrary adjusted.
    • 根据实施例,在恒定周期改变的第一写入使能信号和在字线的激活/停止控制和位线的激活/去激活控制之间的限制时间的时间部分发生变化的第二写使能信号是 多个核心控制信号,其中核心控制信号改变的时间间隔基于输入的第一写入使能信号和第二写入使能信号而局部地短于第一写入使能信号的周期 并且通过使用所生成的核心控制信号来执行电阻性随机存取存储器的操作验证,从而局部地和任意地调整任意测试周期中的周期时间。