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    • 1. 发明授权
    • Wearing article
    • 穿着文章
    • US08663185B2
    • 2014-03-04
    • US12865906
    • 2008-11-20
    • Katsumi MizutaniHaruki TodaMaiko SuzukiYoshikazu Tanaka
    • Katsumi MizutaniHaruki TodaMaiko SuzukiYoshikazu Tanaka
    • A61F13/15
    • A61F13/5644A61F13/49015A61F13/51476A61F13/5148A61F13/5638A61F13/622
    • The present invention aims to provide a wearing article improved so that various types of nonwoven fabrics can be effectively used for target nonwoven fabric without anxiety that the target nonwoven fabric once engaged with hook elements might be readily torn. As an outer sheet 8 defining a garment-facing side of a chassis 2, a commonly-used nonwoven fabric is used and this nonwoven fabric is oriented in a longitudinal direction Y. Rear waist region's side edges 14 of the chassis 2 are provided with flaps 16 attached thereto. Each of the flaps 16 has a joint region 19 along which the flap 16 is joined to the chassis 2 and first and second hook elements 21, 22. Between the joint region 19 and the first and second hook elements 21, 22 as viewed in the transverse direction X, a contractible region 23 adapted to be contractible in the transverse direction X. The contractible region 23 is provided with a plurality of flap's elastic members 24. The joint region 19 provided with none of the flap's elastic members 24 define a non-contractible region. The first and second hook elements 21, 22 of the flap 16 may be put in engagement with the outer sheet 8 to connect the front and rear waist regions 4, 5 to each other in a circumferential direction.
    • 本发明的目的在于提供一种改进的磨损物品,使得各种类型的无纺布能够有效地用于目标无纺布,而不会焦虑地使得一旦与钩元件接合的目标无纺布可能容易被撕裂。 作为限定底盘2的面向衣服侧的外侧片材8,使用常用的无纺布,并且该无纺布沿长度方向Y取向。底座2的后腰围区域的侧边缘14设有翼片 16。 每个翼片16具有接合区域19,翼片16沿着该接合区域19连接到底盘2以及第一和第二钩形元件21,22。在接合区域19和第一和第二钩形元件21,22之间, 横向X,适于在横向方向X收缩的收缩区域23.可收缩区域23设置有多个翼片的弹性构件24.设置有没有翼片的弹性构件24的接合区域19限定非易失性区域, 可收缩区域 翼片16的第一和第二钩形元件21,22可以与外部片8接合,以使前后腰围区域4,5沿圆周方向相互连接。
    • 2. 发明申请
    • WEARING ARTICLE
    • 穿着文章
    • US20110046597A1
    • 2011-02-24
    • US12865906
    • 2008-11-20
    • Katsumi MizutaniHaruki TodaMaiko SuzukiYoshikazu Tanaka
    • Katsumi MizutaniHaruki TodaMaiko SuzukiYoshikazu Tanaka
    • A61F13/49A61F13/62
    • A61F13/5644A61F13/49015A61F13/51476A61F13/5148A61F13/5638A61F13/622
    • The present invention aims to provide a wearing article improved so that various types of nonwoven fabrics can be effectively used for target nonwoven fabric without anxiety that the target nonwoven fabric once engaged with hook elements might be readily torn. As an outer sheet 8 defining a garment-facing side of a chassis 2, a commonly-used nonwoven fabric is used and this nonwoven fabric is oriented in a longitudinal direction Y. Rear waist region's side edges 14 of the chassis 2 are provided with flaps 16 attached thereto. Each of the flaps 16 has a joint region 19 along which the flap 16 is joined to the chassis 2 and first and second hook elements 21, 22. Between the joint region 19 and the first and second hook elements 21, 22 as viewed in the transverse direction X, a contractible region 23 adapted to be contractible in the transverse direction X. The contractible region 23 is provided with a plurality of flap's elastic members 24. The joint region 19 provided with none of the flap's elastic members 24 define a non-contractible region. The first and second hook elements 21, 22 of the flap 16 may be put in engagement with the outer sheet 8 to connect the front and rear waist regions 4, 5 to each other in a circumferential direction.
    • 本发明的目的在于提供一种改进的磨损物品,使得各种类型的无纺布能够有效地用于目标无纺布,而不会焦虑地使得一旦与钩元件接合的目标无纺布可能容易被撕裂。 作为限定底盘2的面向衣服侧的外侧片材8,使用常用的无纺布,并且该无纺布沿长度方向Y取向。底座2的后腰围区域的侧边缘14设有翼片 16。 每个翼片16具有接合区域19,翼片16沿着该接合区域19连接到底盘2以及第一和第二钩形元件21,22。在接合区域19和第一和第二钩形元件21,22之间, 横向X,适于在横向方向X收缩的收缩区域23.可收缩区域23设置有多个翼片的弹性构件24.设置有没有翼片的弹性构件24的接合区域19限定非易失性区域, 可收缩区域 翼片16的第一和第二钩形元件21,22可以与外部片8接合,以使前后腰围区域4,5沿圆周方向相互连接。
    • 5. 发明授权
    • Semiconductor memory device and method of controlling the same
    • 半导体存储器件及其控制方法
    • US08687406B2
    • 2014-04-01
    • US13597740
    • 2012-08-29
    • Haruki Toda
    • Haruki Toda
    • G11C11/00
    • G11C13/0069G11C13/0011G11C13/0023G11C13/004G11C13/0097G11C2213/71G11C2213/73
    • According to an embodiment, a semiconductor memory device comprises: a memory cell array configured having a plurality of memory cell mats, the memory cell mats including a plurality of first lines, second lines, and memory cells, and the memory cell mats being stacked such that the first and second lines are shared alternately by each of the memory cell mats; and a peripheral circuit. Each of the memory cells has a variable resistance characteristic and a current rectifying characteristic. An orientation from an anode toward a cathode of all the memory cells is identical. The peripheral circuit applies to one of the first line and the second line connected to an anode side of the selected memory cell a selected bit line voltage, and applies to the other a selected word line voltage.
    • 根据实施例,半导体存储器件包括:配置有多个存储单元垫的存储单元阵列,所述存储单元阵列包括多个第一行,第二行和存储单元,并且存储单元阵列被堆叠 第一和第二行由每个存储单元垫交替共享; 和外围电路。 每个存储单元具有可变电阻特性和电流整流特性。 从所有存储器单元的阳极到阴极的取向是相同的。 外围电路适用于与所选存储单元的阳极侧连接的选定位线电压的第一线路和第二线路中的一条线路,并且向另一条线路电压施加。
    • 6. 发明申请
    • SEMICONDUCTOR MEMORY DEVICE
    • 半导体存储器件
    • US20140009997A1
    • 2014-01-09
    • US14005149
    • 2012-03-07
    • Haruki Toda
    • Haruki Toda
    • G11C13/00
    • G11C13/003G11C13/0011G11C13/0023G11C13/004G11C2013/0073G11C2213/71G11C2213/72H01L27/115
    • A semiconductor memory device including a memory cell array including a memory cell layer containing plural memory cells operative to store data in accordance with different resistance states; and an access circuit operative to make access to the memory cells, the memory cell changing the resistance state from a first resistance state to a second resistance state on application of a voltage of a first polarity, and changing the resistance state from the second resistance state to the first resistance state on application of a voltage of a second polarity, the access circuit applying voltages, required for access to the memory cell, to first and second lines connected to a selected memory cell, and bringing at least one of the first and second lines connected to non-selected memory cells into the floating state to make access to the selected memory cell.
    • 一种半导体存储器件,包括存储单元阵列,所述存储单元阵列包括存储单元层,所述存储单元层包含多个用于根据不同电阻状态存储数据的存储单元; 以及访问电路,其操作以访问所述存储单元,所述存储单元在施加第一极性的电压时将所述电阻状态从第一电阻状态改变为第二电阻状态,并且从所述第二电阻状态改变所述电阻状态 在施加第二极性的电压的情况下,所述存取电路将访问所述存储单元所需的电压施加到连接到所选择的存储单元的第一和第二行,并且使所述第一和第 连接到未选择的存储器单元的第二行进入浮置状态以访问所选存储单元。
    • 7. 发明授权
    • Resistance change memory device
    • 电阻变化记忆装置
    • US08537595B2
    • 2013-09-17
    • US13231687
    • 2011-09-13
    • Haruki Toda
    • Haruki Toda
    • G11C13/02
    • G11C8/12G11C13/00G11C13/004G11C13/0069G11C2013/0054G11C2013/009G11C2213/71G11C2213/72
    • A resistance change memory device includes: a cell array having multiple layers of mats laminated thereon, each of the mats having word lines and bit lines intersecting each other as well as resistance change type memory cells arranged at intersections thereof, each of the mats further having therein a reference cell and a reference bit line connected to the reference cell, the reference cell set to a state of a certain resistance value; a selection circuit configured to select a word line in each mat of the cell array, and select a bit line intersecting a selected word line and the reference bit line at the same time; and a sense amplifier configured to sense data by comparing respective cell currents of a selected memory cell on the selected bit line and the reference cell on the reference bit line.
    • 一种电阻变化存储器件包括:具有层叠在其上的多层垫的单元阵列,每个垫具有彼此相交的字线和位线以及布置在其交叉处的电阻变化型存储单元,每个垫还具有 其中参考单元和连接到参考单元的参考位线,参考单元设置为一定电阻值的状态; 选择电路,被配置为选择单元阵列的每个矩阵中的字线,并且同时选择与所选择的字线和参考位线相交的位线; 以及读出放大器,被配置为通过比较所选位线上的所选存储单元和参考位线上的参考单元的各个单元电流来检测数据。
    • 10. 发明授权
    • Phase change memory device
    • 相变存储器件
    • US08237143B2
    • 2012-08-07
    • US13217493
    • 2011-08-25
    • Haruki Toda
    • Haruki Toda
    • H01L29/02
    • G11C13/0004G11C5/02G11C7/18G11C13/0007G11C2211/4013G11C2213/31G11C2213/71G11C2213/72H01L27/2409H01L27/2481H01L45/06H01L45/1233
    • A memory device has a semiconductor substrate; a plurality of cell arrays stacked above the substrate, each cell array having memory cells, bit lines each commonly connecting one ends of plural cells arranged along a first direction and word lines each commonly connecting the other ends of plural cells arranged along a second direction; a read/write circuit formed on the substrate as underlying the cell arrays; first and second vertical wiring disposed on both sides of each cell array in the first direction to connect the bit lines to the read/write circuit; and third vertical wirings disposed on both sides of each cell array in the second direction to connect the word lines to the read/write circuit.
    • 存储器件具有半导体衬底; 多个单元阵列,堆叠在基板上方,每个单元阵列具有存储单元,每个通常连接沿着第一方向布置的多个单元的一端的位线和每个共同连接沿着第二方向布置的多个单元的另一端的字线; 在基板上形成的读/写电路,位于单元阵列下面; 第一和第二垂直布线沿着第一方向布置在每个单元阵列的两侧,以将位线连接到读/写电路; 以及在第二方向上设置在每个单元阵列两侧的第三垂直布线,以将字线连接到读/写电路。