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1. 发明授权

US08169807B2 Content addressable memory device having match line equalizer circuit 有权
标题翻译：具有匹配线均衡器电路的内容可寻址存储器件
公开(公告)号：US08169807B2
公开(公告)日：2012-05-01
申请号：US12261598
申请日：2008-10-30
申请人： Katsumi Dosaka , Kazutami Arimoto , Yoshio Matsuda
发明人： Katsumi Dosaka , Kazutami Arimoto , Yoshio Matsuda
IPC分类号： G11C15/00
CPC分类号： G06F17/30982 , G11C15/04 , Y02D10/45
摘要： In a content addressable memory device, before search operations in two TCAM cells connected to first and second match lines, respectively, a memory controller connects the first match line to a power source and connects the second match line to a ground, and then connects the first and second match lines to each other so as that electric potentials of the first and second match lines are the same as each other.
摘要翻译：在内容可寻址存储器件中，在分别连接到第一和第二匹配线的两个TCAM单元中的搜索操作之前，存储器控制器将第一匹配线连接到电源，并将第二匹配线连接到地，然后将第一和第二匹配线彼此之间，使得第一和第二匹配线的电位彼此相同。

2. 发明申请

US20090113122A1 CONTENT ADDRESSABLE MEMORY DEVICE HAVING MATCH LINE EQUALIZER CIRCUIT 有权
标题翻译：具有匹配线路均衡器电路的内容可寻址存储器件
公开(公告)号：US20090113122A1
公开(公告)日：2009-04-30
申请号：US12261598
申请日：2008-10-30
申请人： Katsumi Dosaka , Kazutami Arimoto , Yoshio Matsuda
发明人： Katsumi Dosaka , Kazutami Arimoto , Yoshio Matsuda
IPC分类号： G06F12/00 , G06F17/30
CPC分类号： G06F17/30982 , G11C15/04 , Y02D10/45
摘要： In a content addressable memory device, before search operations in two TCAM cells connected to first and second match lines, respectively, a memory controller connects the first match line to a power source and connects the second match line to a ground, and then connects the first and second match lines to each other so as that electric potentials of the first and second match lines are the same as each other.
摘要翻译：在内容可寻址存储器件中，在分别连接到第一和第二匹配线的两个TCAM单元中的搜索操作之前，存储器控制器将第一匹配线连接到电源，并将第二匹配线连接到地，然后将第一和第二匹配线彼此之间，使得第一和第二匹配线的电位彼此相同。

3. 发明授权

US6075732A Semiconductor memory device with redundancy circuit 失效
标题翻译：具有冗余电路的半导体存储器件
公开(公告)号：US6075732A
公开(公告)日：2000-06-13
申请号：US334917
申请日：1999-06-17
申请人： Tsukasa Ooishi , Yoshio Matsuda , Kazutami Arimoto , Masaki Tsukude , Kazuyasu Fujishima
发明人： Tsukasa Ooishi , Yoshio Matsuda , Kazutami Arimoto , Masaki Tsukude , Kazuyasu Fujishima
IPC分类号： G11C11/413 , G11C7/00 , G11C11/401 , G11C29/00 , G11C29/04 , H01L21/82 , H01L27/10
CPC分类号： G11C29/806 , G11C29/781 , G11C8/10
摘要： A semiconductor memory device comprises two memory cell arrays (1a, 1b) in which a block divisional operation is performed. Two spare rows (2a, 2b) are provided corresponding to the two memory cell arrays (1a, 1b). Spare row decoders (5a, 5b) are provided for selecting the spare rows (2a, 2b), respectively. One spare row decoder selecting signal generation circuit (18) used in common by the spare row decoders (5a, 5b) is provided. The spare row decoder selecting signal generation circuit (18) can be previously set so as to generate a spare row decoder selecting signal (SRE) when a defective row exists in either of the memory cell arrays (1a, 1b) and the defective row is selected by row decoder groups (4a, 4b). Each of the spare row decoders (5a, 5b) is activated in response to the spare row decoder selecting signal (SRE) and a block control signal.
摘要翻译：半导体存储器件包括执行块分割操作的两个存储单元阵列（1a，1b）。对应于两个存储单元阵列（1a，1b）提供两个备用行（2a，2b）。备用排解码器（5a，5b）分别用于选择备用行（2a，2b）。提供了由备用行解码器（5a，5b）共同使用的一个备用行解码器选择信号生成电路（18）。可以预先设置备用行解码器选择信号生成电路（18），以便当在存储单元阵列（1a，1b）中存在缺陷行时产生备用行解码器选择信号（+ E，ovs SRE + EE）），并且由行解码器组（4a，4b）选择有缺陷的行。每个备用行解码器（5a，5b）响应于备用行解码器选择信号（+ E，ovs SRE + EE）和块控制信号被激活。

4. 发明授权

US5504713A Semiconductor memory device with redundancy circuit 失效
标题翻译：具有冗余电路的半导体存储器件
公开(公告)号：US5504713A
公开(公告)日：1996-04-02
申请号：US180166
申请日：1994-01-11
申请人： Tsukasa Ooishi , Yoshio Matsuda , Kazutami Arimoto , Masaki Tsukude , Kazuyasu Fujishima
发明人： Tsukasa Ooishi , Yoshio Matsuda , Kazutami Arimoto , Masaki Tsukude , Kazuyasu Fujishima
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/806 , G11C29/781
摘要： A semiconductor memory device comprises two memory cell arrays (1a, 1b) in which a block divisional operation is performed. Two spare rows (2a, 2b) are provided corresponding to the two memory cell arrays (1a, 1b). Spare row decoders (5a, 5b) are provided for selecting the spare rows (2a, 2b), respectively. One spare row decoder selecting signal generation circuit (18) used in common by the spare row decoders (5a, 5b) is provided. The spare row decoder selecting signal generation circuit (18) can be previously set so as to generate a spare row decoder selecting signal (SRE) when a defective row exists in either of the memory cell arrays (1a, 1b) and the defective row is selected by row decoder groups (4a, 4b). Each of the spare row decoders (5a, 5b) is activated in response to the spare row decoder selecting signal (SRE) and a block control signal.
摘要翻译：半导体存储器件包括执行块分割操作的两个存储单元阵列（1a，1b）。对应于两个存储单元阵列（1a，1b）提供两个备用行（2a，2b）。备用排解码器（5a，5b）分别用于选择备用行（2a，2b）。提供了由备用行解码器（5a，5b）共同使用的一个备用行解码器选择信号生成电路（18）。可以预先设置备用行解码器选择信号生成电路（18），以便当在存储单元阵列（1a，1b）和缺陷行中存在缺陷行时产生备用行解码器选择信号（＆amp; upbar＆S）由行解码器组（4a，4b）选择。每个备用行解码器（5a，5b）响应于备用行解码器选择信号（＆amp; S＆amp; S）和块控制信号被激活。

5. 发明授权

US5136543A Data descrambling in semiconductor memory device 失效
标题翻译：半导体存储器件中的数据解扰
公开(公告)号：US5136543A
公开(公告)日：1992-08-04
申请号：US741208
申请日：1991-07-31
申请人： Yoshio Matsuda , Kazuyasu Fujishima , Kazutami Arimoto , Masaki Tsukude , Tsukasa Oishi
发明人： Yoshio Matsuda , Kazuyasu Fujishima , Kazutami Arimoto , Masaki Tsukude , Tsukasa Oishi
IPC分类号： G11C7/10
CPC分类号： G11C7/1006
摘要： A semiconductor memory device comprises a plurality of bit line pairs and an input/output line pair. Each bit line pair comprises first and second bit lines supplied with complementary data, and the input/output line pair comprises first and second input/output lines supplied with complementary data. A switching circuit is provided on each bit line pair. Each switching circuit, in response to a control signal according to an address signal, respectively couples the first and the second bit lines to the first and the second input/output lines, or inversely, respectively couples the first and the second bit lines to the second and the first input/output lines.
摘要翻译：半导体存储器件包括多个位线对和一个输入/输出线对。每个位线对包括提供有互补数据的第一和第二位线，并且输入/输出线对包括提供有互补数据的第一和第二输入/输出线。在每个位线对上提供开关电路。每个开关电路响应于根据地址信号的控制信号分别将第一和第二位线耦合到第一和第二输入/输出线，或者相反地将第一和第二位线耦合到第二个和第一个输入/输出线。

6. 发明授权

US4873669A Random access memory device operable in a normal mode and in a test mode 失效
标题翻译：随机存取存储器件可在正常模式和测试模式下操作
公开(公告)号：US4873669A
公开(公告)日：1989-10-10
申请号：US77306
申请日：1987-07-24
申请人： Kiyohiro Furutani , Koichiro Mashiko , Kazutami Arimoto , Noriaki Matsumoto , Yoshio Matsuda
发明人： Kiyohiro Furutani , Koichiro Mashiko , Kazutami Arimoto , Noriaki Matsumoto , Yoshio Matsuda
IPC分类号： G11C11/401 , G06F11/267 , G11C7/10 , G11C11/409 , G11C29/00 , G11C29/26 , G11C29/34 , G11C29/38
CPC分类号： G11C7/1057 , G11C29/26 , G11C29/38 , G11C7/10 , G11C7/1006 , G11C7/1051 , G11C7/1078 , G11C7/1084 , G06F11/267
摘要： A semiconductor memory device operable for reading and writing in a normal mode and in a test mode is divided into memory cell sections each having blocks of memory cells. Data bus lines are connected to the respective blocks, and switches interconnect data bus lines connected to blocks of the different sections. The switches are made conductive during reading and writing in the normal mode and during writing in the test mode, and nonconductive during reading in the test mode. Input data are applied onto the data bus lines connected to one of the blocks for writing in the blocks of the sections simultaneously during writing in the normal mode and in the test mode. In the normal mode, data are read out of the blocks of the sections through the data bus lines connected to the above-mentioned one of the blocks. In the test mode, the data are read out of the blocks of the sections through the data bus lines connected to the respective blocks.
摘要翻译：可以以正常模式和测试模式读取和写入的半导体存储器件被分成具有存储单元块的存储单元部分。数据总线连接到相应的块，并且交换连接到不同部分的块的数据总线。读取和写入时，开关在正常模式下和写入期间在测试模式下导通，并且在测试模式下读取期间不导通。在正常模式和测试模式下，输入数据被施加到连接到块之一的数据总线上，用于在写入期间同时在块中写入。在正常模式下，通过连接到上述一个块的数据总线，从这些部分的块中读出数据。在测试模式中，通过连接到相应块的数据总线，从这些部分的块中读出数据。

7. 发明授权

US4833518A Semiconductor memory device having improved interconnection structure of memory cell array 失效
标题翻译：具有改善的存储单元阵列的互连结构的半导体存储器件
公开(公告)号：US4833518A
公开(公告)日：1989-05-23
申请号：US094646
申请日：1987-09-09
申请人： Yoshio Matsuda , Koichiro Mashiko , Kazutami Arimoto , Noriaki Matsumoto , Kiyohiro Furutani
发明人： Yoshio Matsuda , Koichiro Mashiko , Kazutami Arimoto , Noriaki Matsumoto , Kiyohiro Furutani
IPC分类号： H01L27/10 , H01L21/8242 , H01L23/528 , H01L27/108 , H01L29/94
CPC分类号： H01L29/945 , H01L23/528 , H01L27/10805 , H01L27/10829 , H01L2924/0002 , Y10S257/922 , Y10S257/929
摘要： A memory cell array is divided into two groups, one bit line of a pair of bit lines is connected to corresponding memory cells in the first group of the memory cell array, and the other bit line thereof is connected to corresponding memory cells in the second group of the memory cell array.
摘要翻译：存储单元阵列被分成两组，一对位线的一个位线连接到存储单元阵列的第一组中的相应存储单元，而另一位与第二组中的相应存储单元连接组的存储单元阵列。

8. 发明授权

US5894440A Semiconductor memory device and data transferring structure and method therein 失效
标题翻译：半导体存储器件及其数据传输结构及方法
公开(公告)号：US5894440A
公开(公告)日：1999-04-13
申请号：US189276
申请日：1994-01-31
申请人： Masaki Tsukude , Kazutami Arimoto , Kazuyasu Fujishima , Yoshio Matsuda , Tsukasa Ooishi
发明人： Masaki Tsukude , Kazutami Arimoto , Kazuyasu Fujishima , Yoshio Matsuda , Tsukasa Ooishi
IPC分类号： G11C11/401 , G11C7/06 , G11C7/10 , G11C11/409
CPC分类号： G11C7/06 , G11C7/1006 , G11C7/1039
摘要： Each of divided bit line pairs is selectively connected to a sub-input/output line pair through transfer gates. A register is connected to the sub-input/output line pair. Data is transferred through the sub-input/output line pair between the register and a selected bit line pair. A sense amplifier is connected to each of the bit line pairs. Sense amplifiers are independently driven by separate sense amplifier activating signals. Therefore, even if data is transferred to the selected bit line pair from the register, fluctuations in potential on the bit line pair caused in such a case does not affect a sense amplifier activating signal connected to a non-selected bit line pair. As a result, data stored in the non-selected memory cell is prevented from being destroyed.
摘要翻译：每个分开的位线对通过传输门选择性地连接到子输入/输出线对。寄存器连接到子输入/输出线对。数据通过寄存器和所选位线对之间的子输入/输出线对传输。读出放大器连接到每个位线对。感测放大器由独立的读出放大器激活信号驱动。因此，即使数据从寄存器传送到所选择的位线对，在这种情况下引起的位线对上的电位波动也不影响连接到未选位线对的读出放大器激活信号。结果，防止存储在未选择的存储单元中的数据被破坏。

9. 发明授权

US5293598A Random access memory with a plurality of amplifier groups 失效
标题翻译：具有多个放大器组的随机存取存储器
公开(公告)号：US5293598A
公开(公告)日：1994-03-08
申请号：US912135
申请日：1992-07-09
申请人： Kiyohiro Furutani , Koichiro Mashiko , Kazutami Arimoto , Noriaki Matsumoto , Yoshio Matsuda
发明人： Kiyohiro Furutani , Koichiro Mashiko , Kazutami Arimoto , Noriaki Matsumoto , Yoshio Matsuda
IPC分类号： G06F11/267 , G11C7/10 , G11C29/26 , G11C29/38 , G06F13/40
CPC分类号： G11C7/10 , G11C29/26 , G11C29/38 , G11C7/1006 , G11C7/1051 , G11C7/1057 , G11C7/1078 , G11C7/1084 , G06F11/267
摘要： A semiconductor memory device operable for reading and writing in a normal mode and in a test mode is divided into memory cell sections each having blocks of memory cells. Data bus lines are connected to the respective blocks, and switches interconnect data bus lines connected to blocks of the different sections. The switch are made conductive during reading and writing in the normal mode and during writing in the test mode, and nonconductive during reading in the test mode. Input data are applied onto the data bus lines connected one of the blocks for writing in the blocks of the sections simultaneously during writing in the normal mode and in the test mode. In the normal mode, data are read out of the blocks of the sections through the data bus lines connected to the above-mentioned one of the blocks. In the test mode, the data are read out of the blocks of the sections through the data bus lines connected to the respective blocks.
摘要翻译：可以以正常模式和测试模式读取和写入的半导体存储器件被分成具有存储单元块的存储单元部分。数据总线连接到相应的块，并且交换连接到不同部分的块的数据总线。在正常模式下读写时，在测试模式下写入期间开关导通，在测试模式下读取期间不导通。在正常模式和测试模式下，输入数据被加到连接在一个块上的数据总线上，以便在写入期间同时在这些块中写入。在正常模式下，通过连接到上述一个块的数据总线，从这些部分的块中读出数据。在测试模式中，通过连接到相应块的数据总线，从这些部分的块中读出数据。

10. 发明授权

US5267214A Shared-sense amplifier control signal generating circuit in dynamic type semiconductor memory device and operating method therefor 失效
标题翻译：动态型半导体存储器件中的共享感放大器控制信号发生电路及其操作方法
公开(公告)号：US5267214A
公开(公告)日：1993-11-30
申请号：US616264
申请日：1990-11-20
申请人： Kazuyasu Fujishima , Yoshio Matsuda , Kazutami Arimoto , Tsukasa Ooishi , Masaki Tsukude
发明人： Kazuyasu Fujishima , Yoshio Matsuda , Kazutami Arimoto , Tsukasa Ooishi , Masaki Tsukude
IPC分类号： G11C11/409 , G11C11/401 , G11C11/4076 , G11C11/4091 , H01L21/8242 , H01L27/108 , G11C11/34
CPC分类号： G11C11/4091 , G11C11/4076
摘要： A dynamic random access memory amplifier arrangement includes a sense amplifier band shared between two different memory blocks. In this memory, only sense amplifiers related to a selected memory block are activated. The memory comprises a circuit for boosting a control signal voltage to a switching unit for connecting the selected memory block to the sense amplifiers up to a level higher than a power supply voltage Vcc during the activation of the sense amplifiers, and a circuit for separating a memory block paired with the selected memory block from the activated sense amplifiers during the sensing operation. The memory further comprises a circuit for generating a control signal of the power supply voltage Vcc and connecting all the memory blocks to the corresponding sense amplifiers in a stand-by state wherein a row address strobe signal is inactive. With this arrangement, a highly reliable memory consuming less power can be achieved which ensures data writing and/or rewriting at a full Vcc level.
摘要翻译：动态随机存取存储器放大器装置包括在两个不同存储块之间共享的读出放大器带。在该存储器中，只有与所选存储器块相关的读出放大器被激活。存储器包括用于将控制信号电压升压到开关单元的电路，用于在感测放大器的激活期间将选择的存储块连接到读出放大器，直到高于电源电压Vcc的电平，以及用于分离存储块在感测操作期间与所激活的读出放大器与选择的存储块配对。存储器还包括用于产生电源电压Vcc的控制信号的电路，并且在行地址选通信号无效的待机状态下将所有存储块连接到相应的读出放大器。通过这种布置，可以实现消耗更少功率的高度可靠的存储器，其确保在完全Vcc级别的数据写入和/或重写。

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