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1. 发明授权

US07087474B2 Semiconductor device and a method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07087474B2
公开(公告)日：2006-08-08
申请号：US10739319
申请日：2003-12-19
申请人： Katsuhiro Mitsuda , Mitsuharu Honda , Akira Iizuka
发明人： Katsuhiro Mitsuda , Mitsuharu Honda , Akira Iizuka
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L21/823835 , H01L21/02063 , H01L21/26506 , H01L21/26513 , H01L21/324 , H01L21/823814 , H01L29/665 , H01L29/6659 , H01L29/7842
摘要： A method of manufacturing a semiconductor device having a field effect transistor with improved current driving performance (increase of drain current) includes the steps of ion implanting a group IV element from the main surface to the inside of a silicon layer serving as a semiconductor substrate to a level shallower than the implantation depth of the impurities in the step of forming the semiconductor region before the step of ion implanting impurities from the main surface to the inside of the silicon layer serving as a semiconductor substrate so as to form a semiconductor region which is aligned with the gate electrode.
摘要翻译：制造具有提高的电流驱动性能（漏电流的增加）的场效应晶体管的半导体器件的方法包括以下步骤：将IV族元件从用作半导体衬底的硅层的主表面到内部离子注入到在从作为半导体衬底的硅层的主表面到内部的离子注入杂质的步骤之前形成半导体区域的步骤中的杂质的注入深度的水平浅，以形成半导体区域与栅电极对准。

2. 发明授权

US07384834B2 Semiconductor device and a method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07384834B2
公开(公告)日：2008-06-10
申请号：US11411892
申请日：2006-04-27
申请人： Katsuhiro Mitsuda , Mitsuharu Honda , Akira Iizuka
发明人： Katsuhiro Mitsuda , Mitsuharu Honda , Akira Iizuka
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L21/823835 , H01L21/02063 , H01L21/26506 , H01L21/26513 , H01L21/324 , H01L21/823814 , H01L29/665 , H01L29/6659 , H01L29/7842
摘要： A semiconductor device and a method of manufacturing such a semiconductor device having a field effect transistor with improved current driving performance (e.g., an increase of drain current) of the field effect transistor comprising the steps of ion implanting an element from the main surface to the inside of a silicon layer as a semiconductor substrate to a level shallower than the implantation depth of the impurities in the step of forming the semiconductor region before the step of ion implanting impurities from the main surface to the inside of the silicon layer as a semiconductor substrate to form the semiconductor region being aligned with the gate electrode.
摘要翻译：一种半导体器件和制造这种具有场效应晶体管的半导体器件的方法，所述场效应晶体管具有提高的场效应晶体管的电流驱动性能（例如，增加漏极电流），包括以下步骤：将元件从主表面离子注入到在作为半导体衬底的从硅表面到内部的离子注入杂质的步骤之前形成半导体区域的步骤中，将作为半导体衬底的硅层的内部设置为比杂质的注入深度浅的水平以形成与栅电极对准的半导体区域。

3. 发明申请

US20060199323A1 Semiconductor device and a method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060199323A1
公开(公告)日：2006-09-07
申请号：US11411892
申请日：2006-04-27
申请人： Katsuhiro Mitsuda , Mitsuharu Honda , Akira Iizuka
发明人： Katsuhiro Mitsuda , Mitsuharu Honda , Akira Iizuka
IPC分类号： H01L21/8234
CPC分类号： H01L21/823835 , H01L21/02063 , H01L21/26506 , H01L21/26513 , H01L21/324 , H01L21/823814 , H01L29/665 , H01L29/6659 , H01L29/7842
摘要： A semiconductor device and a method of manufacturing such a semiconductor device having a field effect transistor with improved current driving performance (e.g., an increase of drain current) of the field effect transistor comprising the steps of ion implanting an element from the main surface to the inside of a silicon layer as a semiconductor substrate to a level shallower than the implantation depth of the impurities in the step of forming the semiconductor region before the step of ion implanting impurities from the main surface to the inside of the silicon layer as a semiconductor substrate to form the semiconductor region being aligned with the gate electrode.
摘要翻译：一种半导体器件和制造这种具有场效应晶体管的半导体器件的方法，所述场效应晶体管具有提高的场效应晶体管的电流驱动性能（例如，增加漏极电流），包括以下步骤：将元件从主表面离子注入到在作为半导体衬底的从硅表面到内部的离子注入杂质的步骤之前形成半导体区域的步骤中，将作为半导体衬底的硅层的内部设置为比杂质的注入深度浅的水平以形成与栅电极对准的半导体区域。

4. 发明申请

US20080242013A1 SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080242013A1
公开(公告)日：2008-10-02
申请号：US12113467
申请日：2008-05-01
申请人： Katsuhiro Mitsuda , Mitsuharu Honda , Akira Ilzuka
发明人： Katsuhiro Mitsuda , Mitsuharu Honda , Akira Ilzuka
IPC分类号： H01L21/336
CPC分类号： H01L21/26506 , H01L21/02063 , H01L21/26513 , H01L21/2658 , H01L21/324 , H01L21/823814 , H01L21/823835 , H01L29/665 , H01L29/6659 , H01L29/7842
摘要： A semiconductor device and a method of manufacturing such a semiconductor device having a field effect transistor with improved current driving performance (e.g., an increase of drain current) of the field effect transistor comprising the steps of ion implanting an element from the main surface to the inside of a silicon layer as a semiconductor substrate to a level shallower than the implantation depth of the impurities in the step of forming the semiconductor region before the step of ion implanting impurities from the main surface to the inside of the silicon layer as a semiconductor substrate to form the semiconductor region being aligned with the gate electrode.
摘要翻译：一种半导体器件和制造这种具有场效应晶体管的半导体器件的方法，所述场效应晶体管具有提高的场效应晶体管的电流驱动性能（例如，增加漏极电流），包括以下步骤：将元件从主表面离子注入到在作为半导体衬底的从硅表面到内部的离子注入杂质的步骤之前形成半导体区域的步骤中，将作为半导体衬底的硅层的内部设置为比杂质的注入深度浅的水平以形成与栅电极对准的半导体区域。

5. 发明授权

US07871871B2 Manufacturing method for semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件的制造方法
公开(公告)号：US07871871B2
公开(公告)日：2011-01-18
申请号：US12393087
申请日：2009-02-26
申请人： Masanobu Hishiki , Yaichiro Miura , Hiroshi Kawashima , Katsuhiro Mitsuda
发明人： Masanobu Hishiki , Yaichiro Miura , Hiroshi Kawashima , Katsuhiro Mitsuda
IPC分类号： H01L21/66
CPC分类号： H01L21/26513 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L22/12 , H01L29/1083 , H01L2924/0002 , H01L2924/00
摘要： In mass production of CMIS integrated circuit devices or the like, electric characteristics, such as Vth (threshold voltage) or the like, disadvantageously vary due to variations in gate length of the MISFET. This problem has become serious because of a short channel effect. In order to solve the problem, various kinds of feed-forward techniques have been studied in which a subsequent variation factor process is regulated to be reversed with respect to variations in a previous variation factor process so as to cause these variation factors to cancel each other out. Since the feed-back technique has an effect of the cancellation process over the entire system, the technique can be relatively easily applied to a product with a single type of MISFE, but is difficult to be applied to a product equipped with a plurality of types of MISFETs. The invention is adapted to adjust the amount of halo implantation by multivariate analysis based on the result of a patterning step of the gate electrode and a film forming step of an offset spacer.
摘要翻译：在大规模生产CMIS集成电路器件等时，诸如Vth（阈值电压）等的电特性由于MISFET的栅极长度的变化而不利地变化。这个问题已经变得严重，因为通道效应很短。为了解决这个问题，已经研究了各种前馈技术，其中随后的变化因子过程被调整为相对于先前的变化因子过程的变化而被反转，以使这些变化因子相互抵消出来由于反馈技术具有整个系统的取消处理的效果，因此该技术可以相对容易地应用于具有单一类型的MISFE的产品，但是难以应用于配备有多种类型的产品的MISFETs。本发明适用于基于栅电极的图案形成步骤和偏移间隔物的成膜步骤的结果，通过多元分析来调整光晕注入量。

6. 发明申请

US20090221105A1 MANUFACTURING METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：半导体集成电路器件的制造方法
公开(公告)号：US20090221105A1
公开(公告)日：2009-09-03
申请号：US12393087
申请日：2009-02-26
申请人： Masanobu Hishiki , Yaichiro Miura , Hiroshi Kawashima , Katsuhiro Mitsuda
发明人： Masanobu Hishiki , Yaichiro Miura , Hiroshi Kawashima , Katsuhiro Mitsuda
IPC分类号： H01L21/66 , H01L21/8238
CPC分类号： H01L21/26513 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L22/12 , H01L29/1083 , H01L2924/0002 , H01L2924/00
摘要： In mass production of CMIS integrated circuit devices or the like, electric characteristics, such as Vth (threshold voltage) or the like, disadvantageously vary due to variations in gate length of the MISFET. This problem has become serious because of a short channel effect. In order to solve the problem, various kinds of feed-forward techniques have been studied in which a subsequent variation factor process is regulated to be reversed with respect to variations in a previous variation factor process so as to cause these variation factors to cancel each other out. Since the feed-back technique has an effect of the cancellation process over the entire system, the technique can be relatively easily applied to a product with a single type of MISFE, but is difficult to be applied to a product equipped with a plurality of types of MISFETs. The invention is adapted to adjust the amount of halo implantation by multivariate analysis based on the result of a patterning step of the gate electrode and a film forming step of an offset spacer.
摘要翻译：在大规模生产CMIS集成电路器件等时，诸如Vth（阈值电压）等的电特性由于MISFET的栅极长度的变化而不利地变化。这个问题已经变得严重，因为通道效应很短。为了解决这个问题，已经研究了各种前馈技术，其中随后的变化因子过程被调整为相对于先前的变化因子过程的变化而被反转，以使这些变化因子相互抵消出来由于反馈技术具有整个系统的取消处理的效果，因此该技术可以相对容易地应用于具有单一类型的MISFE的产品，但是难以应用于配备有多种类型的产品的MISFETs。本发明适用于基于栅电极的图案形成步骤和偏移间隔物的成膜步骤的结果，通过多元分析来调整光晕注入量。

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