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    • 4. 发明授权
    • Coding apparatus capable of high speed operation
    • 能够高速运行的编码装置
    • US06751773B2
    • 2004-06-15
    • US09833061
    • 2001-04-12
    • Kazuhiro OkabayashiMinoru OkamotoMasayuki Yamasaki
    • Kazuhiro OkabayashiMinoru OkamotoMasayuki Yamasaki
    • H03M1303
    • H03M13/23
    • A coding apparatus includes shift register, input register and logical operation section. The shift register performs bit shifting on an input bit sequence and stores one bit of the input bit sequence after another. The input register stores coefficients of terms on respective orders of a generator polynomial. The logical operation section obtains logical products of the respective bits stored on the shift register and associated bits stored on the input register and a logical product of each one bit input to the shift register and an associated bit stored on the input register so that the earlier a bit of the input bit sequence was input, the higher-order one of the coefficients in the terms of the polynomial the input bit is associated with. Next, the logical operation section derives an exclusive logical sum of the products and then outputs the sum as a bit of a code sequence.
    • 编码装置包括移位寄存器,输入寄存器和逻辑运算部。 移位寄存器在输入位序列上执行位移位,并将输入位序列的一位相继存储。 输入寄存器存储关于生成多项式的各个阶的项的系数。 逻辑运算部分获得存储在移位寄存器上的相应位的逻辑积和存储在输入寄存器上的相关位以及输入到移位寄存器的每一位的逻辑积和存储在输入寄存器上的关联位, 输入一位输入比特序列,输入比特关联的多项式项中的系数中的高阶一个。 接下来,逻辑运算部分导出乘积的异或逻辑和,然后输出和作为代码序列的位。
    • 9. 发明申请
    • Information processing device and information processing method
    • 信息处理装置及信息处理方法
    • US20060095727A1
    • 2006-05-04
    • US11304818
    • 2005-12-16
    • Minoru OkamotoKatsuhiko Ueda
    • Minoru OkamotoKatsuhiko Ueda
    • G06F9/40
    • G06F9/30196G06F9/30181
    • An information processing device for sequentially reading and executing programs stored in memory means, including: a program counter for outputting an address for reading a program to the memory means; an instruction decoder for decoding instructions read from the memory means in response to a control signal indicating a period in which the types of codes used in at least a field among fields constituting an instruction in the program are limited to a predetermined number or less; and controlled means for performing processing corresponding to the decoded results output from the instruction decoder. The instruction decoder has a reconfigurable circuit for changing the circuit configuration in response to the control signal so that the decoding is performed based on a relationship between codes in a field in which the types of codes used are limited and decoded results, the relationship being set so that the number of times of change of bit values in the field is reduced.
    • 一种用于顺序读取和执行存储在存储装置中的程序的信息处理装置,包括:程序计数器,用于将用于读取程序的地址输出到存储装置; 指令解码器,用于响应于指示在构成程序中的指令的至少一个字段中使用的代码的类型被限制为预定数量或更少的周期的控制信号来解码从存储器装置读取的指令; 以及用于执行与从指令解码器输出的解码结果对应的处理的控制装置。 指令解码器具有可重构电路,用于响应于控制信号改变电路配置,使得基于所使用的代码的类型的码中的码之间的关系进行解码,并且解码结果,该关系被设置 使得字段中比特值的改变次数减少。