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1. 发明申请

US20110309333A1 SEMICONDUCTOR DEVICES FABRICATED BY DOPED MATERIAL LAYER AS DOPANT SOURCE 有权
标题翻译：由掺杂材料层组成的半导体器件作为掺杂源
公开(公告)号：US20110309333A1
公开(公告)日：2011-12-22
申请号：US12819440
申请日：2010-06-21
申请人： Kangguo Cheng , Bruce B. Doris , Balasubramanian S. Haran , Ali Khakifirooz , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Balasubramanian S. Haran , Ali Khakifirooz , Ghavam G. Shahidi
IPC分类号： H01L29/775 , H01L21/34 , H01L27/12 , H01L21/84
CPC分类号： H01L29/785 , B82Y10/00 , H01L21/2254 , H01L21/2255 , H01L21/2257 , H01L21/823418 , H01L21/823425 , H01L21/823481 , H01L21/823814 , H01L21/823878 , H01L21/84 , H01L21/845 , H01L27/1211 , H01L29/165 , H01L29/42392 , H01L29/66439 , H01L29/665 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/66772 , H01L29/66803 , H01L29/775 , H01L29/78 , H01L29/7833 , H01L29/7834 , H01L29/7848 , H01L29/78696
摘要： A method of forming a semiconductor device is provided, in which the dopant for the source and drain regions is introduced from a doped dielectric layer. In one example, a gate structure is formed on a semiconductor layer of an SOI substrate, in which the thickness of the semiconductor layer is less than 10 nm. A doped dielectric layer is formed over at least the portion of the semiconductor layer that is adjacent to the gate structure. The dopant from the doped dielectric layer is driven into the portion of the semiconductor layer that is adjacent to the gate structure. The dopant diffused into the semiconductor provides source and drain extension regions.
摘要翻译：提供一种形成半导体器件的方法，其中用于源极和漏极区的掺杂剂从掺杂的介电层引入。在一个示例中，栅极结构形成在半导体层的厚度小于10nm的SOI衬底的半导体层上。在与栅极结构相邻的半导体层的至少一部分上形成掺杂介电层。来自掺杂介电层的掺杂剂被驱动到与栅极结构相邻的半导体层的部分中。扩散到半导体中的掺杂剂提供了源极和漏极延伸区域。

2. 发明申请

US20120292705A1 SEMICONDUCTOR STRUCTURE HAVING UNDERLAPPED DEVICES 失效
标题翻译：具有底层设备的半导体结构
公开(公告)号：US20120292705A1
公开(公告)日：2012-11-22
申请号：US13108290
申请日：2011-05-16
申请人： Kangguo Cheng , Bruce B. Doris , Balasubramanian S. Haran , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Balasubramanian S. Haran , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L27/092
CPC分类号： H01L27/1203 , H01L21/823864 , H01L21/823892
摘要： A semiconductor structure which includes a semiconductor on insulator (SOI) substrate. The SOI substrate includes a base semiconductor layer; a buried oxide (BOX) layer in contact with the base semiconductor layer; and an SOI layer in contact with the BOX layer. The semiconductor structure further includes a circuit formed with respect to the SOI layer, the circuit including an N type field effect transistor (NFET) having source and drain extensions in the SOI layer and a gate; and a P type field effect transistor (PFET) having source and drain extensions in the SOI layer and a gate. There may also be a well under each of the NFET and PFET. There is a nonzero electrical bias being applied to the. SOI substrate. One of the NFET extensions and PFET extensions may be underlapped with respect to the NFET gate or PFET gate, respectively.
摘要翻译：一种半导体结构，其包括绝缘体上半导体（SOI）基板。 SOI衬底包括基极半导体层; 与基底半导体层接触的掩埋氧化物（BOX）层; 以及与BOX层接触的SOI层。半导体结构还包括相对于SOI层形成的电路，该电路包括在SOI层中具有源极和漏极延伸的N型场效应晶体管（NFET）和栅极; 以及在SOI层中具有源极和漏极延伸的P型场效应晶体管（PFET）和栅极。每个NFET和PFET下面也可以有一个阱。有一个非零的电偏压被施加到。 SOI衬底。 NFET扩展和PFET扩展中的一个可能分别相对于NFET栅极或PFET栅极被覆盖。

3. 发明申请

US20120256260A1 DUAL-DEPTH SELF-ALIGNED ISOLATION STRUCTURE FOR A BACK GATE ELECTRODE 失效
标题翻译：用于背盖电极的双深度自对准隔离结构
公开(公告)号：US20120256260A1
公开(公告)日：2012-10-11
申请号：US13082491
申请日：2011-04-08
申请人： Kangguo Cheng , Balasubramanian S. Haran , Ali Khakifirooz , Ghavam G. Shahidi
发明人： Kangguo Cheng , Balasubramanian S. Haran , Ali Khakifirooz , Ghavam G. Shahidi
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66742 , H01L21/26506 , H01L21/2652 , H01L21/26586 , H01L21/743 , H01L21/76229 , H01L21/84 , H01L27/1203 , H01L29/78648
摘要： Doped semiconductor back gate regions self-aligned to active regions are formed by first patterning a top semiconductor layer and a buried insulator layer to form stacks of a buried insulator portion and a semiconductor portion. Oxygen is implanted into an underlying semiconductor layer at an angle so that oxygen-implanted regions are formed in areas that are not shaded by the stack or masking structures thereupon. The oxygen implanted portions are converted into deep trench isolation structures that are self-aligned to sidewalls of the active regions, which are the semiconductor portions in the stacks. Dopant ions are implanted into the portions of the underlying semiconductor layer between the deep trench isolation structures to form doped semiconductor back gate regions. A shallow trench isolation structure is formed on the deep trench isolation structures and between the stacks.
摘要翻译：通过首先构图顶部半导体层和掩埋绝缘体层来形成与有源区域自对准的掺杂半导体背栅极区域，以形成埋入绝缘体部分和半导体部分的堆叠。将氧气以一定角度注入到下面的半导体层中，使得注氧区域形成在不被叠层或掩模结构遮蔽的区域中。氧注入部分被转换成深沟槽隔离结构，其与作为堆叠中的半导体部分的有源区的侧壁自对准。将掺杂离子注入深沟槽隔离结构之间的底层半导体层的部分，以形成掺杂半导体背栅区。在深沟槽隔离结构和堆叠之间形成浅沟槽隔离结构。

4. 发明授权

US08598663B2 Semiconductor structure having NFET and PFET formed in SOI substrate with underlapped extensions 失效
标题翻译：具有NFET和PFET的半导体结构形成在具有延伸延伸的SOI衬底中
公开(公告)号：US08598663B2
公开(公告)日：2013-12-03
申请号：US13108290
申请日：2011-05-16
申请人： Kangguo Cheng , Bruce B. Doris , Balasubramanian S. Haran , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Balasubramanian S. Haran , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L27/12 , H01L21/02 , H01L29/786 , H01L21/70
CPC分类号： H01L27/1203 , H01L21/823864 , H01L21/823892
摘要： A semiconductor structure which includes a semiconductor on insulator (SOI) substrate. The SOI substrate includes a base semiconductor layer; a buried oxide (BOX) layer in contact with the base semiconductor layer; and an SOI layer in contact with the BOX layer. The semiconductor structure further includes a circuit formed with respect to the SOI layer, the circuit including an N type field effect transistor (NFET) having source and drain extensions in the SOI layer and a gate; and a P type field effect transistor (PFET) having source and drain extensions in the SOI layer and a gate. There may also be a well under each of the NFET and PFET. There is a nonzero electrical bias being applied to the SOI substrate. One of the NFET extensions and PFET extensions may be underlapped with respect to the NFET gate or PFET gate, respectively.
摘要翻译：一种半导体结构，其包括绝缘体上半导体（SOI）基板。 SOI衬底包括基极半导体层; 与基底半导体层接触的掩埋氧化物（BOX）层; 以及与BOX层接触的SOI层。半导体结构还包括相对于SOI层形成的电路，该电路包括在SOI层中具有源极和漏极延伸的N型场效应晶体管（NFET）和栅极; 以及在SOI层中具有源极和漏极延伸的P型场效应晶体管（PFET）和栅极。每个NFET和PFET下面也可以有一个阱。存在将非零电偏压施加到SOI衬底。 NFET扩展和PFET扩展中的一个可能分别相对于NFET栅极或PFET栅极被覆盖。

5. 发明授权

US08394710B2 Semiconductor devices fabricated by doped material layer as dopant source 有权
标题翻译：由掺杂材料层制造的半导体器件作为掺杂剂源
公开(公告)号：US08394710B2
公开(公告)日：2013-03-12
申请号：US12819440
申请日：2010-06-21
申请人： Kangguo Cheng , Bruce B. Doris , Balasubramanian S. Haran , Ali Khakifirooz , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Balasubramanian S. Haran , Ali Khakifirooz , Ghavam G. Shahidi
IPC分类号： H01L21/22 , H01L21/38
CPC分类号： H01L29/785 , B82Y10/00 , H01L21/2254 , H01L21/2255 , H01L21/2257 , H01L21/823418 , H01L21/823425 , H01L21/823481 , H01L21/823814 , H01L21/823878 , H01L21/84 , H01L21/845 , H01L27/1211 , H01L29/165 , H01L29/42392 , H01L29/66439 , H01L29/665 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/66772 , H01L29/66803 , H01L29/775 , H01L29/78 , H01L29/7833 , H01L29/7834 , H01L29/7848 , H01L29/78696
摘要： A method of forming a semiconductor device is provided, in which the dopant for the source and drain regions is introduced from a doped dielectric layer. In one example, a gate structure is formed on a semiconductor layer of an SOI substrate, in which the thickness of the semiconductor layer is less than 10 nm. A doped dielectric layer is formed over at least the portion of the semiconductor layer that is adjacent to the gate structure. The dopant from the doped dielectric layer is driven into the portion of the semiconductor layer that is adjacent to the gate structure. The dopant diffused into the semiconductor provides source and drain extension regions.
摘要翻译：提供一种形成半导体器件的方法，其中用于源极和漏极区的掺杂剂从掺杂的介电层引入。在一个示例中，栅极结构形成在半导体层的厚度小于10nm的SOI衬底的半导体层上。在与栅极结构相邻的半导体层的至少一部分上形成掺杂介电层。来自掺杂介电层的掺杂剂被驱动到与栅极结构相邻的半导体层的部分中。扩散到半导体中的掺杂剂提供了源极和漏极延伸区域。

6. 发明授权

US08399957B2 Dual-depth self-aligned isolation structure for a back gate electrode 失效
标题翻译：用于背栅电极的双深度自对准隔离结构
公开(公告)号：US08399957B2
公开(公告)日：2013-03-19
申请号：US13082491
申请日：2011-04-08
申请人： Kangguo Cheng , Balasubramanian S. Haran , Ali Khakifirooz , Ghavam G. Shahidi
发明人： Kangguo Cheng , Balasubramanian S. Haran , Ali Khakifirooz , Ghavam G. Shahidi
IPC分类号： H01L29/06
CPC分类号： H01L29/66742 , H01L21/26506 , H01L21/2652 , H01L21/26586 , H01L21/743 , H01L21/76229 , H01L21/84 , H01L27/1203 , H01L29/78648
摘要： Doped semiconductor back gate regions self-aligned to active regions are formed by first patterning a top semiconductor layer and a buried insulator layer to form stacks of a buried insulator portion and a semiconductor portion. Oxygen is implanted into an underlying semiconductor layer at an angle so that oxygen-implanted regions are formed in areas that are not shaded by the stack or masking structures thereupon. The oxygen implanted portions are converted into deep trench isolation structures that are self-aligned to sidewalls of the active regions, which are the semiconductor portions in the stacks. Dopant ions are implanted into the portions of the underlying semiconductor layer between the deep trench isolation structures to form doped semiconductor back gate regions. A shallow trench isolation structure is formed on the deep trench isolation structures and between the stacks.
摘要翻译：通过首先构图顶部半导体层和掩埋绝缘体层来形成与有源区域自对准的掺杂半导体背栅极区域，以形成埋入绝缘体部分和半导体部分的堆叠。将氧气以一定角度注入到下面的半导体层中，使得注氧区域形成在不被叠层或掩模结构遮蔽的区域中。氧注入部分被转换成深沟槽隔离结构，其与作为堆叠中的半导体部分的有源区的侧壁自对准。将掺杂离子注入深沟槽隔离结构之间的底层半导体层的部分，以形成掺杂半导体背栅区。在深沟槽隔离结构和堆叠之间形成浅沟槽隔离结构。

7. 发明授权

US09048108B2 Integrated circuit with on chip planar diode and CMOS devices 有权
标题翻译：集成电路与片上平面二极管和CMOS器件
公开(公告)号：US09048108B2
公开(公告)日：2015-06-02
申请号：US13478080
申请日：2012-05-22
申请人： Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L21/8238 , H01L27/06
CPC分类号： H01L27/0629 , H01L29/0847 , H01L29/8611 , H01L29/868
摘要： An electrical circuit, planar diode, and method of forming a diode and one or more CMOS devices on the same chip. The method includes electrically isolating a portion of a substrate in a diode region from other substrate regions. The method also includes recessing the substrate in the diode region. The method further includes epitaxially forming in the diode region a first doped layer above the substrate and epitaxially forming in the diode region a second doped layer above the first doped layer.
摘要翻译：在同一芯片上形成二极管和一个或多个CMOS器件的电路，平面二极管和方法。该方法包括将二极管区域中的衬底的一部分与其它衬底区域电隔离。该方法还包括使二极管区域中的衬底凹陷。该方法还包括在二极管区域中外延形成在衬底上方的第一掺杂层，并在二极管区域中外延地形成第一掺杂层上方的第二掺杂层。

8. 发明授权

US08652898B2 Integrated circuit with a thin body field effect transistor and capacitor 失效
标题翻译：具有薄体场效应晶体管和电容器的集成电路
公开(公告)号：US08652898B2
公开(公告)日：2014-02-18
申请号：US13614908
申请日：2012-09-13
申请人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Ghavam G. Shahidi
IPC分类号： H01L21/77
CPC分类号： H01L21/84 , H01L21/32053 , H01L21/823814 , H01L27/0629 , H01L27/1203 , H01L29/41783
摘要： A transistor region of a first semiconductor layer and a capacitor region in the first semiconductor layer are isolated. A dummy gate structure is formed on the first semiconductor layer in the transistor region. A second semiconductor layer is formed on the first semiconductor layer. First and second portions of the second semiconductor layer are located in the transistor region, and a third portion of the second semiconductor layer is located in the capacitor region. First, second, and third silicide regions are formed on the first, second, and third portions of the second semiconductor layer, respectively. After forming a dielectric layer, the dummy gate structure is removed forming a first cavity. At least a portion of the dielectric layer located above the third silicide region is removed forming a second cavity. A gate dielectric is formed in the first cavity and a capacitor dielectric in the second cavity.
摘要翻译：隔离第一半导体层中的第一半导体层和电容器区域的晶体管区域。在晶体管区域的第一半导体层上形成虚拟栅极结构。在第一半导体层上形成第二半导体层。第二半导体层的第一和第二部分位于晶体管区域中，第二半导体层的第三部分位于电容器区域中。第一，第二和第三硅化物区分别形成在第二半导体层的第一，第二和第三部分上。在形成电介质层之后，去除伪栅极结构形成第一腔。位于第三硅化物区域上方的电介质层的至少一部分被去除，形成第二腔。在第一腔中形成栅极电介质，在第二腔中形成电容器电介质。

9. 发明申请

US20130313651A1 INTEGRATED CIRCUIT WITH ON CHIP PLANAR DIODE AND CMOS DEVICES 有权
公开(公告)号：US20130313651A1
公开(公告)日：2013-11-28
申请号：US13478080
申请日：2012-05-22
申请人： Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L27/07 , H01L21/8238
CPC分类号： H01L27/0629 , H01L29/0847 , H01L29/8611 , H01L29/868
摘要： An electrical circuit, planar diode, and method of forming a diode and one or more CMOS devices on the same chip. The method includes electrically isolating a portion of a substrate in a diode region from other substrate regions. The method also includes recessing the substrate in the diode region. The method further includes epitaxially forming in the diode region a first doped layer above the substrate and epitaxially forming in the diode region a second doped layer above the first doped layer.

10. 发明授权

US08318574B2 SOI trench DRAM structure with backside strap 有权
标题翻译：具有背面带的SOI沟槽DRAM结构
公开(公告)号：US08318574B2
公开(公告)日：2012-11-27
申请号：US12847208
申请日：2010-07-30
申请人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L21/20
CPC分类号： H01L27/1203 , H01L27/10829 , H01L27/10867
摘要： In one exemplary embodiment, a semiconductor structure including: a SOI substrate having of a top silicon layer overlying an insulation layer, the insulation layer overlies a bottom silicon layer; a capacitor disposed at least partially in the insulation layer; a device disposed at least partially on the top silicon layer, where the device is coupled to a doped portion of the top silicon layer; a backside strap of first epitaxially-deposited material, at least a first portion of the backside strap underlies the doped portion of the top silicon layer, the backside strap is coupled to the doped portion of the top silicon layer at a first end of the backside strap and to the capacitor at a second end of the backside strap; and second epitaxially-deposited material that at least partially overlies the doped portion of the top silicon layer, the second epitaxially-deposited material further at least partially overlies the first portion.
摘要翻译：在一个示例性实施例中，一种半导体结构，包括：具有覆盖绝缘层的顶部硅层的SOI衬底，所述绝缘层覆盖在底部硅层上; 至少部分地设置在绝缘层中的电容器; 至少部分地设置在所述顶部硅层上的器件，其中所述器件耦合到所述顶部硅层的掺杂部分; 第一外延沉积材料的背面带，背侧带的至少第一部分位于顶部硅层的掺杂部分的下面，背面带在背面的第一端耦合到顶部硅层的掺杂部分带子和背部带子的第二端处的电容器; 以及至少部分地覆盖在顶部硅层的掺杂部分上的第二外延沉积材料，第二外延沉积材料还至少部分地覆盖在第一部分上。

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