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1. 发明授权

US08652898B2 Integrated circuit with a thin body field effect transistor and capacitor 失效
标题翻译：具有薄体场效应晶体管和电容器的集成电路
公开(公告)号：US08652898B2
公开(公告)日：2014-02-18
申请号：US13614908
申请日：2012-09-13
申请人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Ghavam G. Shahidi
IPC分类号： H01L21/77
CPC分类号： H01L21/84 , H01L21/32053 , H01L21/823814 , H01L27/0629 , H01L27/1203 , H01L29/41783
摘要： A transistor region of a first semiconductor layer and a capacitor region in the first semiconductor layer are isolated. A dummy gate structure is formed on the first semiconductor layer in the transistor region. A second semiconductor layer is formed on the first semiconductor layer. First and second portions of the second semiconductor layer are located in the transistor region, and a third portion of the second semiconductor layer is located in the capacitor region. First, second, and third silicide regions are formed on the first, second, and third portions of the second semiconductor layer, respectively. After forming a dielectric layer, the dummy gate structure is removed forming a first cavity. At least a portion of the dielectric layer located above the third silicide region is removed forming a second cavity. A gate dielectric is formed in the first cavity and a capacitor dielectric in the second cavity.
摘要翻译：隔离第一半导体层中的第一半导体层和电容器区域的晶体管区域。在晶体管区域的第一半导体层上形成虚拟栅极结构。在第一半导体层上形成第二半导体层。第二半导体层的第一和第二部分位于晶体管区域中，第二半导体层的第三部分位于电容器区域中。第一，第二和第三硅化物区分别形成在第二半导体层的第一，第二和第三部分上。在形成电介质层之后，去除伪栅极结构形成第一腔。位于第三硅化物区域上方的电介质层的至少一部分被去除，形成第二腔。在第一腔中形成栅极电介质，在第二腔中形成电容器电介质。

2. 发明授权

US08659066B2 Integrated circuit with a thin body field effect transistor and capacitor 有权
标题翻译：具有薄体场效应晶体管和电容器的集成电路
公开(公告)号：US08659066B2
公开(公告)日：2014-02-25
申请号：US13345266
申请日：2012-01-06
申请人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Ghavam G. Shahidi
IPC分类号： H01L27/06
CPC分类号： H01L21/84 , H01L21/32053 , H01L21/823814 , H01L27/0629 , H01L27/1203 , H01L29/41783
摘要： An integrated circuit includes a transistor and a capacitor. The transistor includes a first semiconductor layer and a gate stack located on the first semiconductor layer. The gate stack includes a metal layer and a first high-k dielectric layer. A gate spacer is located on sidewalls of the gate stack. The first high-k dielectric layer is located between the first semiconductor layer and the metal layer and between the gate spacer and sidewalls of the metal layer. A first silicide region is located on a first source/drain region. A second silicide region is located on a second source/drain region. The capacitor includes a first terminal that comprises a third silicide region located on a portion of the second semiconductor. A second high-k dielectric layer is located on the silicide region. A second terminal comprises a metal layer that is located on the second high-k dielectric layer.
摘要翻译：集成电路包括晶体管和电容器。晶体管包括位于第一半导体层上的第一半导体层和栅极堆叠。栅堆叠包括金属层和第一高k电介质层。栅极间隔物位于栅极叠层的侧壁上。第一高k电介质层位于第一半导体层和金属层之间以及栅间隔物和金属层的侧壁之间。第一硅化物区域位于第一源极/漏极区域上。第二硅化物区域位于第二源极/漏极区域上。电容器包括第一端子，其包括位于第二半导体的一部分上的第三硅化物区域。第二高k电介质层位于硅化物区域上。第二端子包括位于第二高k电介质层上的金属层。

3. 发明申请

US20130175596A1 INTEGRATED CIRCUIT WITH A THIN BODY FIELD EFFECT TRANSISTOR AND CAPACITOR 有权
标题翻译：具有薄体场效应晶体管和电容器的集成电路
公开(公告)号：US20130175596A1
公开(公告)日：2013-07-11
申请号：US13345266
申请日：2012-01-06
申请人： Kangguo CHENG , Bruce Doris , Ali Khakifirooz , Ghavam G. Shahidi
发明人： Kangguo CHENG , Bruce Doris , Ali Khakifirooz , Ghavam G. Shahidi
IPC分类号： H01L27/06 , H01L21/8234
CPC分类号： H01L21/84 , H01L21/32053 , H01L21/823814 , H01L27/0629 , H01L27/1203 , H01L29/41783
摘要： An integrated circuit includes a transistor and a capacitor. The transistor includes a first semiconductor layer and a gate stack located on the first semiconductor layer. The gate stack includes a metal layer and a first high-k dielectric layer. A gate spacer is located on sidewalls of the gate stack. The first high-k dielectric layer is located between the first semiconductor layer and the metal layer and between the gate spacer and sidewalls of the metal layer. A first silicide region is located on a first source/drain region. A second silicide region is located on a second source/drain region. The capacitor includes a first terminal that comprises a third silicide region located on a portion of the second semiconductor. A second high-k dielectric layer is located on the silicide region. A second terminal comprises a metal layer that is located on the second high-k dielectric layer.
摘要翻译：集成电路包括晶体管和电容器。晶体管包括位于第一半导体层上的第一半导体层和栅极堆叠。栅堆叠包括金属层和第一高k电介质层。栅极间隔物位于栅极叠层的侧壁上。第一高k电介质层位于第一半导体层和金属层之间以及栅间隔物和金属层的侧壁之间。第一硅化物区域位于第一源极/漏极区域上。第二硅化物区域位于第二源极/漏极区域上。电容器包括第一端子，其包括位于第二半导体的一部分上的第三硅化物区域。第二高k电介质层位于硅化物区域上。第二端子包括位于第二高k电介质层上的金属层。

4. 发明授权

US09048108B2 Integrated circuit with on chip planar diode and CMOS devices 有权
标题翻译：集成电路与片上平面二极管和CMOS器件
公开(公告)号：US09048108B2
公开(公告)日：2015-06-02
申请号：US13478080
申请日：2012-05-22
申请人： Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L21/8238 , H01L27/06
CPC分类号： H01L27/0629 , H01L29/0847 , H01L29/8611 , H01L29/868
摘要： An electrical circuit, planar diode, and method of forming a diode and one or more CMOS devices on the same chip. The method includes electrically isolating a portion of a substrate in a diode region from other substrate regions. The method also includes recessing the substrate in the diode region. The method further includes epitaxially forming in the diode region a first doped layer above the substrate and epitaxially forming in the diode region a second doped layer above the first doped layer.
摘要翻译：在同一芯片上形成二极管和一个或多个CMOS器件的电路，平面二极管和方法。该方法包括将二极管区域中的衬底的一部分与其它衬底区域电隔离。该方法还包括使二极管区域中的衬底凹陷。该方法还包括在二极管区域中外延形成在衬底上方的第一掺杂层，并在二极管区域中外延地形成第一掺杂层上方的第二掺杂层。

5. 发明申请

US20130313651A1 INTEGRATED CIRCUIT WITH ON CHIP PLANAR DIODE AND CMOS DEVICES 有权
公开(公告)号：US20130313651A1
公开(公告)日：2013-11-28
申请号：US13478080
申请日：2012-05-22
申请人： Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L27/07 , H01L21/8238
CPC分类号： H01L27/0629 , H01L29/0847 , H01L29/8611 , H01L29/868
摘要： An electrical circuit, planar diode, and method of forming a diode and one or more CMOS devices on the same chip. The method includes electrically isolating a portion of a substrate in a diode region from other substrate regions. The method also includes recessing the substrate in the diode region. The method further includes epitaxially forming in the diode region a first doped layer above the substrate and epitaxially forming in the diode region a second doped layer above the first doped layer.

6. 发明授权

US08318574B2 SOI trench DRAM structure with backside strap 有权
标题翻译：具有背面带的SOI沟槽DRAM结构
公开(公告)号：US08318574B2
公开(公告)日：2012-11-27
申请号：US12847208
申请日：2010-07-30
申请人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L21/20
CPC分类号： H01L27/1203 , H01L27/10829 , H01L27/10867
摘要： In one exemplary embodiment, a semiconductor structure including: a SOI substrate having of a top silicon layer overlying an insulation layer, the insulation layer overlies a bottom silicon layer; a capacitor disposed at least partially in the insulation layer; a device disposed at least partially on the top silicon layer, where the device is coupled to a doped portion of the top silicon layer; a backside strap of first epitaxially-deposited material, at least a first portion of the backside strap underlies the doped portion of the top silicon layer, the backside strap is coupled to the doped portion of the top silicon layer at a first end of the backside strap and to the capacitor at a second end of the backside strap; and second epitaxially-deposited material that at least partially overlies the doped portion of the top silicon layer, the second epitaxially-deposited material further at least partially overlies the first portion.
摘要翻译：在一个示例性实施例中，一种半导体结构，包括：具有覆盖绝缘层的顶部硅层的SOI衬底，所述绝缘层覆盖在底部硅层上; 至少部分地设置在绝缘层中的电容器; 至少部分地设置在所述顶部硅层上的器件，其中所述器件耦合到所述顶部硅层的掺杂部分; 第一外延沉积材料的背面带，背侧带的至少第一部分位于顶部硅层的掺杂部分的下面，背面带在背面的第一端耦合到顶部硅层的掺杂部分带子和背部带子的第二端处的电容器; 以及至少部分地覆盖在顶部硅层的掺杂部分上的第二外延沉积材料，第二外延沉积材料还至少部分地覆盖在第一部分上。

7. 发明申请

US20120286364A1 Integrated Circuit Diode 有权
标题翻译：集成电路二极管
公开(公告)号：US20120286364A1
公开(公告)日：2012-11-15
申请号：US13104542
申请日：2011-05-10
申请人： Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L27/12 , H01L21/8238
CPC分类号： H01L27/0727 , H01L21/823418 , H01L21/84 , H01L27/0629 , H01L27/1203
摘要： A method includes forming isolation regions in a semiconductor substrate to define a first field effect transistor (FET) region, a second FET region, and a diode region, forming a first gate stack in the first FET region and a second gate stack in the second FET region, forming a layer of spacer material over the second FET region and the second gate stack, forming a first source region and a first drain region in the first FET region and a first diode layer in the diode region using a first epitaxial growth process, forming a hardmask layer over the first source region, the first drain region, the first gate stack and a portion of the first diode layer, and forming a second source region and a second drain region in the first FET region and a second diode layer on the first diode layer using a second epitaxial growth process.
摘要翻译：一种方法包括在半导体衬底中形成隔离区以限定第一场效应晶体管（FET）区域，第二FET区域和二极管区域，在第一FET区域中形成第一栅极堆叠，在第二FET区域中形成第二栅极堆叠 FET区域，在所述第二FET区域和所述第二栅极堆叠上形成间隔材料层，在所述第一FET区域中形成第一源极区域和第一漏极区域，以及使用第一外延生长工艺在所述二极管区域中形成第一二极管层在所述第一源极区域，所述第一漏极区域，所述第一栅极堆叠层和所述第一二极管层的一部分上形成硬掩模层，以及在所述第一FET区域中形成第二源极区域和第二漏极区域，以及在所述第一FET区域中形成第二二极管层使用第二外延生长工艺在第一二极管层上。

8. 发明申请

US20120286350A1 TUNNEL FIELD EFFECT TRANSISTOR 失效
标题翻译：隧道场效应晶体管
公开(公告)号：US20120286350A1
公开(公告)日：2012-11-15
申请号：US13558518
申请日：2012-07-26
申请人： Bruce B. Doris , Kangguo Cheng , Wilfried E. Haensch , Ali Khakifirooz , Isaac Lauer , Ghavam G. Shahidi
发明人： Bruce B. Doris , Kangguo Cheng , Wilfried E. Haensch , Ali Khakifirooz , Isaac Lauer , Ghavam G. Shahidi
IPC分类号： H01L29/78
CPC分类号： H01L21/26586 , H01L29/665 , H01L29/66636 , H01L29/66659 , H01L29/78
摘要： An FET device characterized as being an asymmetrical tunnel FET (TFET) is disclosed. The TFET includes a gate-stack, a channel region underneath the gate-stack, a first and a second junction adjoining the gate-stack and being capable for electrical continuity with the channel. The first junction and the second junction are of different conductivity types. The TFET also includes spacer formations in a manner that the spacer formation on one side of the gate-stack is thinner than on the other side.
摘要翻译：公开了一种以不对称隧道FET（TFET）为特征的FET器件。 TFET包括栅极堆叠，栅极堆叠下方的沟道区域，邻接栅极叠层的第一和第二结，并且能够与沟道电连接。第一接头和第二接头具有不同的导电类型。 TFET还包括间隔物结构，使得栅极叠层的一侧上的间隔物形成比另一侧更薄。

9. 发明申请

US20120261757A1 STRAINED THIN BODY CMOS DEVICE HAVING VERTICALLY RAISED SOURCE/DRAIN STRESSORS WITH SINGLE SPACER 有权
标题翻译：具有单个间距的垂直源/源压应力的应变薄体CMOS器件
公开(公告)号：US20120261757A1
公开(公告)日：2012-10-18
申请号：US13531053
申请日：2012-06-22
申请人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L29/78 , H01L27/092
CPC分类号： H01L29/66477 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/1203 , H01L29/66628 , H01L29/66772 , H01L29/7848 , H01L29/78618
摘要： A method of forming a transistor device includes forming a patterned gate structure over a semiconductor substrate; forming a spacer layer over the semiconductor substrate and patterned gate structure; removing horizontally disposed portions of the spacer layer so as to form a vertical sidewall spacer adjacent the patterned gate structure; and forming a raised source/drain (RSD) structure over the semiconductor substrate and adjacent the vertical sidewall spacer, wherein the RSD structure has a substantially vertical sidewall profile so as to abut the vertical sidewall spacer and produce one of a compressive and a tensile strain on a channel region of the semiconductor substrate below the patterned gate structure.
摘要翻译：一种形成晶体管器件的方法包括在半导体衬底上形成图案化栅极结构; 在半导体衬底上形成间隔层和图案化栅极结构; 去除间隔层的水平设置部分，以形成邻近图案化栅极结构的垂直侧壁间隔物; 以及在所述半导体衬底上并且邻近所述垂直侧壁间隔物形成升高的源极/漏极（RSD）结构，其中所述RSD结构具有基本上垂直的侧壁轮廓，以便邻接所述垂直侧壁间隔物并产生压缩和拉伸应变之一在图案化的栅极结构下方的半导体衬底的沟道区上。

10. 发明申请

US20120235239A1 HYBRID MOSFET STRUCTURE HAVING DRAIN SIDE SCHOTTKY JUNCTION 有权
标题翻译：具有排水侧肖特基结的混合MOSFET结构
公开(公告)号：US20120235239A1
公开(公告)日：2012-09-20
申请号：US13049491
申请日：2011-03-16
申请人： Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L27/12 , H01L21/336 , H01L29/78
CPC分类号： H01L21/84 , H01L21/26506 , H01L21/26586 , H01L21/823814 , H01L21/823878 , H01L29/7839
摘要： A method of forming a transistor device includes forming a patterned gate structure over a semiconductor substrate, forming a raised source region over the semiconductor substrate adjacent a source side of the gate structure, and forming silicide contacts on the raised source region, on the patterned gate structure, and on the semiconductor substrate adjacent a drain side of the gate structure. Thereby, a hybrid field effect transistor (FET) structure having a drain side Schottky contact and a raised source side ohmic contact is defined.
摘要翻译：一种形成晶体管器件的方法包括在半导体衬底上形成图案化的栅极结构，在邻近栅极结构的源极侧的半导体衬底上形成凸起的源极区域，并在图案化的栅极上形成凸起的源极区域上的硅化物接触并且在与栅极结构的漏极侧相邻的半导体衬底上。因此，限定了具有漏极侧肖特基接触和升高的源极侧欧姆接触的混合场效应晶体管（FET）结构。

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