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1. 发明授权

US07511535B2 Fine-grained power management of synchronous and asynchronous datapath circuits 有权
标题翻译：同步和异步数据路径电路的细粒度电源管理
公开(公告)号：US07511535B2
公开(公告)日：2009-03-31
申请号：US11680225
申请日：2007-02-28
申请人： Kanad Chakraborty , Steven E. Strauss , Bingxiong Xu
发明人： Kanad Chakraborty , Steven E. Strauss , Bingxiong Xu
IPC分类号： H03K19/00
CPC分类号： H03K19/0016
摘要： A power management circuit is provided for controlling power dissipation in at least one combinational logic circuit. The power management circuit includes a detector operative to receive at least a first input signal to the combinational logic circuit and to detect a transition of the first input signal between a first logic state and a second logic state. The detector generates a control signal indicative of whether or not a transition of the first input signal has occurred. The power management circuit further includes a controller operative to receive the first control signal generated by the detector and to selectively disconnect the first combinational logic circuit from a power supply to the first combinational logic circuit when no logic transition of the first input signal is detected between a preceding computational cycle and a present computational cycle of the first combinational logic circuit, and to connect the first combinational logic circuit to the power supply when a logic transition of the first input signal is detected.
摘要翻译：提供功率管理电路用于控制至少一个组合逻辑电路中的功率耗散。功率管理电路包括检测器，其操作以将至少第一输入信号接收到组合逻辑电路并检测第一逻辑状态和第二逻辑状态之间的第一输入信号的转变。检测器产生指示是否已经发生第一输入信号的转变的控制信号。电源管理电路还包括控制器，其操作以接收由检测器产生的第一控制信号，并且当在第一组合逻辑电路之间没有检测到第一输入信号的逻辑转换时，选择性地将第一组合逻辑电路与电源切断到第一组合逻辑电路第一组合逻辑电路的前述计算周期和当前计算周期，并且当检测到第一输入信号的逻辑转换时，将第一组合逻辑电路连接到电源。

2. 发明申请

US20080204124A1 Fine-Grained Power Management of Synchronous and Asynchronous Datapath Circuits 有权
标题翻译：同步和异步数据路径电路的细粒度电源管理
公开(公告)号：US20080204124A1
公开(公告)日：2008-08-28
申请号：US11680225
申请日：2007-02-28
申请人： Kanad Chakraborty , Steven E. Strauss , Bingxiong Xu
发明人： Kanad Chakraborty , Steven E. Strauss , Bingxiong Xu
IPC分类号： G05F1/10
CPC分类号： H03K19/0016
摘要： A power management circuit is provided for controlling power dissipation in at least one combinational logic circuit. The power management circuit includes a detector operative to receive at least a first input signal to the combinational logic circuit and to detect a transition of the first input signal between a first logic state and a second logic state. The detector generates a control signal indicative of whether or not a transition of the first input signal has occurred. The power management circuit further includes a controller operative to receive the first control signal generated by the detector and to selectively disconnect the first combinational logic circuit from a power supply to the first combinational logic circuit when no logic transition of the first input signal is detected between a preceding computational cycle and a present computational cycle of the first combinational logic circuit, and to connect the first combinational logic circuit to the power supply when a logic transition of the first input signal is detected.
摘要翻译：提供功率管理电路用于控制至少一个组合逻辑电路中的功率耗散。功率管理电路包括检测器，其操作以将至少第一输入信号接收到组合逻辑电路并检测第一逻辑状态和第二逻辑状态之间的第一输入信号的转变。检测器产生指示是否已经发生第一输入信号的转变的控制信号。电源管理电路还包括控制器，其操作以接收由检测器产生的第一控制信号，并且当在第一组合逻辑电路之间没有检测到第一输入信号的逻辑转换时，选择性地将第一组合逻辑电路与电源切断到第一组合逻辑电路第一组合逻辑电路的前述计算周期和当前计算周期，并且当检测到第一输入信号的逻辑转换时，将第一组合逻辑电路连接到电源。

3. 发明授权

US07409659B2 System and method for suppressing crosstalk glitch in digital circuits 失效
标题翻译：抑制数字电路串扰毛刺的系统和方法
公开(公告)号：US07409659B2
公开(公告)日：2008-08-05
申请号：US10988083
申请日：2004-11-12
申请人： Kanad Chakraborty , Thaddeus J. Gabara , Kevin R. Stiles , Bingxiong Xu
发明人： Kanad Chakraborty , Thaddeus J. Gabara , Kevin R. Stiles , Bingxiong Xu
IPC分类号： G06F17/50 , H03K17/16 , H03K19/003 , H01L25/00
CPC分类号： G06F17/505
摘要： A static latch circuit is used to suppress crosstalk glitch in a synchronous digital integrated circuit. A static latch is inserted into a selected victim net, and the net is examined if crosstalk glitch induced in the selected victim net is sufficiently suppressed. If not, then the selected victim net is examined to check whether the crosstalk glitch is primarily due to propagated noise from an earlier stage or due to noise injected in the selected victim net. If the crosstalk glitch is propagated from an earlier stage, then a second static latch is inserted before the state in which the first static latch is inserted. Alternatively, another static latch may be inserted in the selected victim net. Cell libraries including a variety of static latch circuit architectures can be designed.
摘要翻译：静态锁存电路用于抑制同步数字集成电路中的串扰毛刺。将静态锁存器插入到所选择的受害网络中，并且如果被选择的受害者网络中引起的串扰毛刺被充分抑制，则检查网络。如果不是，则检查所选择的受害网络以检查串扰毛刺是否主要是由于来自较早阶段的传播噪声或由于在所选择的受害者网络中注入的噪声引起的。如果从较早阶段传播串扰毛刺，则在插入第一静态锁存器的状态之前插入第二静态锁存器。或者，可以在所选择的受害网络中插入另一个静态锁存器。可以设计包括各种静态锁存电路架构的单元库。

4. 发明申请

US20070194453A1 Integrated circuit architecture for reducing interconnect parasitics 审中-公开
标题翻译：用于减少互连寄生效应的集成电路架构
公开(公告)号：US20070194453A1
公开(公告)日：2007-08-23
申请号：US11341747
申请日：2006-01-27
申请人： Kanad Chakraborty , Bingxiong Xu , Xingling Zhou
发明人： Kanad Chakraborty , Bingxiong Xu , Xingling Zhou
IPC分类号： H01L23/52 , H01L23/48 , H01L29/40
CPC分类号： H01L24/10 , H01L23/49575 , H01L24/13 , H01L25/18 , H01L2224/13 , H01L2224/13099 , H01L2224/16145 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2924/01033 , H01L2924/01077 , H01L2924/01322 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/1433 , H01L2924/00014 , H01L2924/00
摘要： An integrated circuit includes a first semiconductor chip including one or more circuits thereon performing substantially core logic functions, the first semiconductor chip including multiple signal pads for providing electrical connection to the one or more circuits. The integrated circuit further includes at least a second semiconductor chip including one or more circuits thereon performing substantially input/output interface functions, the second semiconductor chip including multiple signal pads for providing electrical connection to the one or more circuits on the first semiconductor chip. The signal pads on the second semiconductor chip are substantially aligned with and electrically connected to corresponding signal pads on the first semiconductor chip. The first and second semiconductor chips are mutually functionally dependent on one another, such that at least a portion of at least one of the one or more circuits on the first semiconductor chip utilizes at least a portion of at least one of the one or more circuits on the second semiconductor chip, and vice versa. The first and second semiconductor chips are formed using first and second semiconductor fabrication processes, respectively.
摘要翻译：集成电路包括第一半导体芯片，其包括其上执行基本上核心逻辑功能的一个或多个电路，所述第一半导体芯片包括用于提供与所述一个或多个电路的电连接的多个信号焊盘。集成电路还包括至少第二半导体芯片，其包括在其上执行基本输入/输出接口功能的一个或多个电路，第二半导体芯片包括用于提供与第一半导体芯片上的一个或多个电路的电连接的多个信号焊盘。第二半导体芯片上的信号焊盘与第一半导体芯片上的相应的信号焊盘基本对准并电连接。第一和第二半导体芯片在功能上彼此相互依赖，使得第一半导体芯片上的一个或多个电路中的至少一个电路的至少一部分利用一个或多个电路中的至少一个电路的至少一部分在第二个半导体芯片上，反之亦然。第一和第二半导体芯片分别使用第一和第二半导体制造工艺形成。

5. 发明申请

US20060107245A1 System and method for suppressing crosstalk glitch in digital circuits 失效
标题翻译：抑制数字电路串扰毛刺的系统和方法
公开(公告)号：US20060107245A1
公开(公告)日：2006-05-18
申请号：US10988083
申请日：2004-11-12
申请人： Kanad Chakraborty , Thaddeus Gabara , Kevin Stiles , Bingxiong Xu
发明人： Kanad Chakraborty , Thaddeus Gabara , Kevin Stiles , Bingxiong Xu
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/505
摘要： A static latch circuit is used to suppress crosstalk glitch in a synchronous digital integrated circuit. A static latch is inserted into a selected victim net, and the net is examined if crosstalk glitch induced in the selected victim net is sufficiently suppressed. If not, then the selected victim net is examined to check whether the crosstalk glitch is primarily due to propagated noise from an earlier stage or due to noise injected in the selected victim net. If the crosstalk glitch is propagated from an earlier stage, then a second static latch is inserted before the state in which the first static latch is inserted. Alternatively, another static latch may be inserted in the selected victim net. Cell libraries including a variety of static latch circuit architectures can be designed.
摘要翻译：静态锁存电路用于抑制同步数字集成电路中的串扰毛刺。将静态锁存器插入到所选择的受害网络中，并且如果被选择的受害者网络中引起的串扰毛刺被充分抑制，则检查网络。如果不是，则检查所选择的受害网络以检查串扰毛刺是否主要是由于来自较早阶段的传播噪声或由于在所选择的受害者网络中注入的噪声引起的。如果从较早阶段传播串扰毛刺，则在插入第一静态锁存器的状态之前插入第二静态锁存器。或者，可以在所选择的受害网络中插入另一个静态锁存器。可以设计包括各种静态锁存电路结构的单元库。

6. 发明授权

US06532578B2 Method of configuring integrated circuits using greedy algorithm for partitioning of N points in P isothetic rectangles 失效
公开(公告)号：US06532578B2
公开(公告)日：2003-03-11
申请号：US09858825
申请日：2001-05-16
申请人： Kanad Chakraborty , Maharaj Mukherjee
发明人： Kanad Chakraborty , Maharaj Mukherjee
IPC分类号： G06F1750
CPC分类号： G06F17/5072
摘要： A method of configuring partitions for different circuit or other operational areas on an integrated circuit initially identifies points representing components of an integrated circuit with respect to a coordinate system having a horizontal axis and a vertical axis, and subsequently creates a first isothetic rectangular partition containing all of the identified points of the integrated circuit. The method then continues by subdividing the first isothetic rectangular partition with respect to the horizontal axis by creating a plurality of isothetic rectangular sub-partitions collectively containing all of the identified points of the integrated circuit. Each of the isothetic rectangular sub-partitions is separated by a line parallel to the horizontal axis. These isothetic rectangular sub-partitions collectively encompass a minimum area containing all of the identified points. The method also includes subdividing the first isothetic rectangular partition with respect to the vertical axis by creating a plurality of isothetic rectangular sub-partitions collectively containing all of the identified points of the integrated circuit. Each of the isothetic rectangular sub-partitions is separated by a line parallel to the vertical axis. These isothetic rectangular sub-partitions collectively encompass a minimum area containing all of the identified points. The method then includes comparing the collective area of the isothetic rectangular sub-partitions subdivided with respect to the horizontal axis to the collective area of the isothetic rectangular sub-partitions subdivided with respect to the vertical axis, and determining which of the horizontally divided or vertically divided isothetic rectangular sub-partitions have the smaller area. The method includes configuring the operational area on the integrated circuit in conformance with the isothetic rectangular sub-partitions determined to have the smaller area.

7. 发明授权

US07047163B1 Method and apparatus for applying fine-grained transforms during placement synthesis interaction 失效
标题翻译：在放置合成相互作用期间应用细粒度变换的方法和装置
公开(公告)号：US07047163B1
公开(公告)日：2006-05-16
申请号：US09524408
申请日：2000-03-13
申请人： Kanad Chakraborty , Wilm Ernst Donath , Prabhakar Nandavar Kudva , Lakshmi Narasimha Reddy , Leon Stok , Andrew James Sullivan , Paul Gerard Villarrubia
发明人： Kanad Chakraborty , Wilm Ernst Donath , Prabhakar Nandavar Kudva , Lakshmi Narasimha Reddy , Leon Stok , Andrew James Sullivan , Paul Gerard Villarrubia
IPC分类号： G06F17/10 , G06F7/60 , G06F15/18 , G06G7/00 , G06N3/00
CPC分类号： G06F17/5045 , G06F17/5072
摘要： A method (and system) of applying transforms for modifying a plurality of domains concurrently in a design space, includes creating a sequence of more and less granular placement and netlist modification transforms. A converging design process flow is created by a flexible mechanism in which a select combination of fine-grained transforms are applied to optimize the netlist and placement of a design.
摘要翻译：在设计空间中同时应用用于修改多个域的变换的方法（和系统）包括创建越来越少的粒度位置和网表修改变换的序列。融合设计流程由灵活的机制创建，其中应用细粒度变换的选择组合来优化设计的网表和布局。

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