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1. 发明授权

US06459317B1 Sense amplifier flip-flop 有权
标题翻译：感应放大器触发器
公开(公告)号：US06459317B1
公开(公告)日：2002-10-01
申请号：US09733250
申请日：2000-12-08
申请人： Kan Lu , Chongjun June Jiang , Uming U. Ko
发明人： Kan Lu , Chongjun June Jiang , Uming U. Ko
IPC分类号： H03K3037
CPC分类号： G11C11/4091 , G11C7/065 , H03K3/356139
摘要： A flip-flop (14) is disclosed that includes an input circuit (50), a sense amplifier (52) and an output circuit (56). The input circuit (50) is operable to receive a data input signal and to generate complementary data signals. The sense amplifier (52) is coupled to the input circuit (50). The sense amplifier (52) is operable to receive the data signals from the input circuit (50) and to generate complementary amplified signals based on the data signals. The output circuit (56) is coupled to the sense amplifier (52). The output circuit (56) is operable to receive the amplified signals from the sense amplifier (52) and to generate complementary output signals based on the amplified signals.
摘要翻译：公开了一种触发器（14），其包括输入电路（50），读出放大器（52）和输出电路（56）。输入电路（50）可操作以接收数据输入信号并产生补充数据信号。读出放大器（52）耦合到输入电路（50）。读出放大器（52）可操作以从输入电路（50）接收数据信号，并根据数据信号生成互补的放大信号。输出电路（56）耦合到读出放大器（52）。输出电路（56）可操作以从读出放大器（52）接收放大的信号，并且基于放大的信号产生互补的输出信号。

2. 发明申请

US20090262588A1 POWER SAVINGS WITH A LEVEL-SHIFTING BOUNDARY ISOLATION FLIP-FLOP (LSIFF) AND A CLOCK CONTROLLED DATA RETENTION SCHEME 有权
标题翻译：具有水平移位边界隔离开关（LSIFF）和时钟控制数据保持方案的节电
公开(公告)号：US20090262588A1
公开(公告)日：2009-10-22
申请号：US12104580
申请日：2008-04-17
申请人： RAMAPRASATH VILANGUDIPITCHAI , Sumanth Katte Gururajarao , Hugh T. Mair , Alice Wang , Uming U. Ko , Sushma Honnavara-Prasad
发明人： RAMAPRASATH VILANGUDIPITCHAI , Sumanth Katte Gururajarao , Hugh T. Mair , Alice Wang , Uming U. Ko , Sushma Honnavara-Prasad
IPC分类号： G11C7/00
CPC分类号： H03K3/356147 , H03K3/0375
摘要： An apparatus for providing active mode power reduction for circuits having data retention includes a master slave flip flop (MSFF) for latching a data input. An output level shifter (OLS), coupled to the MSFF, retains the data input in response to the MSFF being operable in an active power saving mode (APSM) to reduce power. The OLS operating in the APSM provides a level shifter output having a configurable voltage, thereby providing output isolation. A change in an operating mode of the MSFF between an active mode and the APSM is independent of a retention (RET) mode input.
摘要翻译：用于为具有数据保持的电路提供主动模式功率降低的装置包括用于锁存数据输入的主从触发器（MSFF）。耦合到MSFF的输出电平移位器（OLS）保留数据输入以响应MSFF在有功功率节省模式（APSM）中可操作以降低功率。在APSM中操作的OLS提供具有可配置电压的电平移位器输出，从而提供输出隔离。在主动模式和APSM之间的MSFF操作模式的改变与保留（RET）模式输入无关。

3. 发明授权

US06532514B1 System and method for handling a power supply interruption in a non-volatile memory 有权
标题翻译：用于处理非易失性存储器中的电源中断的系统和方法
公开(公告)号：US06532514B1
公开(公告)日：2003-03-11
申请号：US09713564
申请日：2000-11-15
申请人： Baher S. Haroun , Uming U. Ko
发明人： Baher S. Haroun , Uming U. Ko
IPC分类号： G06F1200
CPC分类号： G11C16/30 , G11C16/22
摘要： A system for handling a power supply interruption in a non-volatile memory (10) is disclosed that includes a status indicator set (20) for each sector (16) of a non-volatile memory array (14). The status indicator set (20) is operable to indicate a status for the sector (16) and is independently erasable from the sector (16). A state machine (30) is operable to perform operations on the sectors (16). The state machine (30) is also operable to adjust the status indicator set (20) for a sector (16) prior to performing an operation on the sector (16) to indicate an interruption status and to adjust the status indicator set (20) for the sector (16) after completing the operation to indicate a completed status. Status indicator set (20) preferably includes alternatively employed active indicator sub-sets and erase indicator sub-sets.
摘要翻译：公开了一种用于处理非易失性存储器（10）中的电源中断的系统，其包括用于非易失性存储器阵列（14）的每个扇区（16）的状态指示器组（20）。状态指示器组（20）可操作以指示扇区（16）的状态，并且可独立地从扇区（16）中擦除。状态机（30）可操作以对扇区（16）执行操作。状态机（30）还可操作以在对扇区（16）执行操作之前调整扇区（16）的状态指示器组（20）以指示中断状态并且调整状态指示器组（20）对于扇区（16），完成操作以指示完成状态。状态指示器组（20）优选地包括可选择的使用的主动指示符子集和擦除指示符子集。

4. 发明授权

US08266464B2 Power controller, a method of operating the power controller and a semiconductor memory system employing the same 有权
标题翻译：功率控制器，操作功率控制器的方法和采用该功率控制器的半导体存储器系统
公开(公告)号：US08266464B2
公开(公告)日：2012-09-11
申请号：US11876600
申请日：2007-10-22
申请人： Michael P. Clinton , Keerthinarayan P. Heragu , Uming U. Ko
发明人： Michael P. Clinton , Keerthinarayan P. Heragu , Uming U. Ko
IPC分类号： G06F1/32
CPC分类号： G11C5/147
摘要： Embodiments of the present disclosure provide a power controller, a method of operating a power controller and a semiconductor memory system. In one embodiment, the power controller is for use with a memory and includes an access module configured to provide an active state of the memory to allow memory access. The power controller also includes a retain-till-access module configured to cycle a portion of the memory between the active state and a low leakage data retention state of the memory. The power controller further includes an expanded retain-till-access module configured to extend the active state of the memory for a specified period of time before returning the memory to the low leakage data retention state.
摘要翻译：本公开的实施例提供了功率控制器，操作功率控制器和半导体存储器系统的方法。在一个实施例中，功率控制器用于存储器并且包括被配置为提供存储器的活动状态以允许存储器访问的访问模块。功率控制器还包括保留直到访问模块，其被配置为在存储器的活动状态和低泄漏数据保持状态之间循环存储器的一部分。功率控制器还包括扩展的保留直到访问模块，其被配置为在将存储器返回到低泄漏数据保持状态之前将存储器的活动状态延长指定的时间段。

5. 发明授权

US07376038B2 Fast access memory architecture 有权
标题翻译：快速访问内存架构
公开(公告)号：US07376038B2
公开(公告)日：2008-05-20
申请号：US11385151
申请日：2006-03-21
申请人： Sudha Thiruvengadam , Ramaprasath Vilangudipitchai , David B. Scott , Uming U. Ko , Alice Wang
发明人： Sudha Thiruvengadam , Ramaprasath Vilangudipitchai , David B. Scott , Uming U. Ko , Alice Wang
IPC分类号： G11C5/14
CPC分类号： G11C8/10
摘要： A computer system including a control logic and a storage coupled to the control logic. The storage includes a plurality of bitcells and bitlines used to transfer data between the control logic and the bitcells. The control logic provides an address of a target bitcell to the storage. Within a single clock cycle, the storage uses the address to activate the target bitcell, to precharge bitlines coupled to the target bitcell, and to access the target bitcell.
摘要翻译：一种包括控制逻辑和耦合到控制逻辑的存储器的计算机系统。存储器包括用于在控制逻辑和位单元之间传送数据的多个比特单元和位线。控制逻辑向存储器提供目标位单元的地址。在单个时钟周期内，存储器使用地址来激活目标比特单元，以预先耦合到目标比特单元的位线，并访问目标比特单元。

6. 发明授权

US07307471B2 Adaptive voltage control and body bias for performance and energy optimization 有权
标题翻译：用于性能和能量优化的自适应电压控制和体偏置
公开(公告)号：US07307471B2
公开(公告)日：2007-12-11
申请号：US11213477
申请日：2005-08-26
申请人： Gordon Gammie , Alice Wang , Uming U. Ko , David B. Scott
发明人： Gordon Gammie , Alice Wang , Uming U. Ko , David B. Scott
IPC分类号： G05F1/565
CPC分类号： H03K19/0008 , H03K19/00384
摘要： A device for adaptively controlling a voltage supplied to circuitry in close proximity to the device, comprising a processing module and a first tracking element coupled to the processing module. The first tracking element produces a first value indicative of a first estimated speed associated with the circuitry. The device also comprises a second tracking element coupled to the processing module. The second tracking element produces a second value indicative of a second estimated speed associated with the circuitry. The processing module compares each of the first and second values to respective target values and causes a voltage output to be adjusted based on the comparisons. The first and second tracking elements comprise a plurality of transistors, at least some of the transistors selectively provided with a transistor bias voltage to adjust transistor speed.
摘要翻译：一种用于自适应地控制提供给设备附近的电路的电压的装置，包括耦合到处理模块的处理模块和第一跟踪元件。第一跟踪元件产生指示与电路相关联的第一估计速度的第一值。该装置还包括耦合到处理模块的第二跟踪元件。第二跟踪元件产生指示与电路相关联的第二估计速度的第二值。处理模块将第一和第二值中的每一个与各自的目标值进行比较，并且基于比较使得电压输出被调整。第一和第二跟踪元件包括多个晶体管，至少一些晶体管选择性地提供晶体管偏置电压以调整晶体管速度。

7. 发明授权

US07622955B2 Power savings with a level-shifting boundary isolation flip-flop (LSIFF) and a clock controlled data retention scheme 有权
标题翻译：功率节省与电平移位边界隔离触发器（LSIFF）和时钟控制的数据保留方案
公开(公告)号：US07622955B2
公开(公告)日：2009-11-24
申请号：US12104580
申请日：2008-04-17
申请人： Ramaprasath Vilangudipitchai , Sumanth Katte Gururajarao , Hugh T. Mair , Alice Wang , Uming U. Ko , Sushma Honnavara-Prasad
发明人： Ramaprasath Vilangudipitchai , Sumanth Katte Gururajarao , Hugh T. Mair , Alice Wang , Uming U. Ko , Sushma Honnavara-Prasad
IPC分类号： H03K19/094
CPC分类号： H03K3/356147 , H03K3/0375
摘要： An apparatus for providing active mode power reduction for circuits having data retention includes a master slave flip flop (MSFF) for latching a data input. An output level shifter (OLS), coupled to the MSFF, retains the data input in response to the MSFF being operable in an active power saving mode (APSM) to reduce power. The OLS operating in the APSM provides a level shifter output having a configurable voltage, thereby providing output isolation. A change in an operating mode of the MSFF between an active mode and the APSM is independent of a retention (RET) mode input.
摘要翻译：用于为具有数据保持的电路提供主动模式功率降低的装置包括用于锁存数据输入的主从触发器（MSFF）。耦合到MSFF的输出电平移位器（OLS）保留数据输入以响应MSFF在有功功率节省模式（APSM）中可操作以降低功率。在APSM中操作的OLS提供具有可配置电压的电平移位器输出，从而提供输出隔离。在主动模式和APSM之间的MSFF操作模式的改变与保留（RET）模式输入无关。

8. 发明申请

US20080098244A1 POWER CONTROLLER, A METHOD OF OPERATING THE POWER CONTROLLER AND A SEMICONDUCTOR MEMORY SYSTEM EMPLOYING THE SAME 有权
标题翻译：功率控制器，操作功率控制器的方法和使用其的半导体存储器系统
公开(公告)号：US20080098244A1
公开(公告)日：2008-04-24
申请号：US11876600
申请日：2007-10-22
申请人： Michael P. Clinton , Keerthinarayan P. Heragu , Uming U. Ko
发明人： Michael P. Clinton , Keerthinarayan P. Heragu , Uming U. Ko
IPC分类号： G06F1/32
CPC分类号： G11C5/147
摘要： Embodiments of the present disclosure provide a power controller, a method of operating a power controller and a semiconductor memory system. In one embodiment, the power controller is for use with a memory and includes an access module configured to provide an active state of the memory to allow memory access. The power controller also includes a retain-till-access module configured to cycle a portion of the memory between the active state and a low leakage data retention state of the memory. The power controller further includes an expanded retain-till-access module configured to extend the active state of the memory for a specified period of time before returning the memory to the low leakage data retention state.
摘要翻译：本公开的实施例提供了功率控制器，操作功率控制器和半导体存储器系统的方法。在一个实施例中，功率控制器用于存储器并且包括被配置为提供存储器的活动状态以允许存储器访问的访问模块。功率控制器还包括保留直到访问模块，其被配置为在存储器的活动状态和低泄漏数据保持状态之间循环存储器的一部分。功率控制器还包括扩展的保留直到访问模块，其被配置为在将存储器返回到低泄漏数据保持状态之前将存储器的活动状态延长指定的时间段。

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