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1. 发明申请

US20130086542A1 METHOD AND APPARATUS FOR PATTERN ADJUSTED TIMING VIA PATTERN MATCHING 有权
标题翻译：用于通过图案匹配进行图形调整时序的方法和装置
公开(公告)号：US20130086542A1
公开(公告)日：2013-04-04
申请号：US13251437
申请日：2011-10-03
申请人： Kah Ching Edward Teoh , Vito Dai
发明人： Kah Ching Edward Teoh , Vito Dai
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5081 , G06F2217/84
摘要： An approach is provided for pattern adjusted timing via pattern matching. Embodiments include receiving data corresponding to a problematic layout pattern associated with at least one performance characteristic and data corresponding to an integrated circuit layout design, scanning the integrated circuit layout design for the problematic layout pattern, identifying at least one portion of the integrated circuit layout design substantially matching the problematic layout pattern, and modifying a netlist associated with the integrated circuit layout design, the modification being based on the at least one performance characteristic.
摘要翻译：通过图案匹配为图案调整定时提供了一种方法。实施例包括接收对应于与至少一个性能特征相关联的有问题的布局图案的数据和对应于集成电路布局设计的数据，扫描有问题的布局图案的集成电路布局设计，识别集成电路布局设计的至少一部分基本上匹配有问题的布局图案，以及修改与集成电路布局设计相关联的网表，修改基于至少一个性能特征。

2. 发明授权

US08453089B2 Method and apparatus for pattern adjusted timing via pattern matching 有权
标题翻译：通过模式匹配进行模式调整定时的方法和装置
公开(公告)号：US08453089B2
公开(公告)日：2013-05-28
申请号：US13251437
申请日：2011-10-03
申请人： Kah Ching Edward Teoh , Vito Dai
发明人： Kah Ching Edward Teoh , Vito Dai
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5081 , G06F2217/84
摘要： An approach is provided for pattern adjusted timing via pattern matching. Embodiments include receiving data corresponding to a problematic layout pattern associated with at least one performance characteristic and data corresponding to an integrated circuit layout design, scanning the integrated circuit layout design for the problematic layout pattern, identifying at least one portion of the integrated circuit layout design substantially matching the problematic layout pattern, and modifying a netlist associated with the integrated circuit layout design, the modification being based on the at least one performance characteristic.
摘要翻译：通过图案匹配为图案调整定时提供了一种方法。实施例包括接收对应于与至少一个性能特征相关联的有问题的布局图案的数据和对应于集成电路布局设计的数据，扫描有问题的布局图案的集成电路布局设计，识别集成电路布局设计的至少一部分基本上匹配有问题的布局图案，以及修改与集成电路布局设计相关联的网表，修改基于至少一个性能特征。

3. 发明授权

US08555215B2 Methods for decomposing circuit design layouts and for fabricating semiconductor devices using decomposed patterns 有权
标题翻译：分解电路设计布局和使用分解模式制造半导体器件的方法
公开(公告)号：US08555215B2
公开(公告)日：2013-10-08
申请号：US13400445
申请日：2012-02-20
申请人： Yi Zou , Swamy Maddu , Lynn T. Wang , Vito Dai , Luigi Capodieci , Peng Xie
发明人： Yi Zou , Swamy Maddu , Lynn T. Wang , Vito Dai , Luigi Capodieci , Peng Xie
IPC分类号： G06F17/50
CPC分类号： G03F1/70
摘要： Methods for fabricating semiconductor devices are provided. In an embodiment, a method of fabricating a semiconductor device includes scanning a circuit design layout and proposing patterns for decomposed layouts. The proposed patterns are then compared with a library of prior patterns including a category of forbidden patterns and a category of preferred patterns. If a selected proposed pattern matches a forbidden pattern, the selected proposed pattern is eliminated. If the selected proposed pattern matches a preferred pattern, then the selected proposed pattern is identified for use in the decomposed layouts. Decomposed layouts are generated from the identified patterns. A plurality of masks is fabricated based on the decomposed layouts. Then a multiple patterning lithographic technique is performed with the plurality of masks on a semiconductor substrate.
摘要翻译：提供制造半导体器件的方法。在一个实施例中，制造半导体器件的方法包括扫描电路设计布局并提出用于分解布局的图案。然后将所提出的模式与包括禁止模式类别和优选模式类别的先前模式的库进行比较。如果所选择的提议模式匹配禁止模式，则删除所选择的提议模式。如果所选择的提出的模式匹配优选模式，则所选择的提出的模式被识别用于分解的布局。分辨的布局是从识别的图案生成的。基于分解的布局制造多个掩模。然后用半导体衬底上的多个掩模进行多重图形化光刻技术。

4. 发明授权

US08924896B2 Automated design layout pattern correction based on context-aware patterns 有权
标题翻译：基于上下文感知模式的自动设计布局模式校正
公开(公告)号：US08924896B2
公开(公告)日：2014-12-30
申请号：US13755374
申请日：2013-01-31
申请人： Lynn Wang , Vito Dai , Luigi Capodieci
发明人： Lynn Wang , Vito Dai , Luigi Capodieci
IPC分类号： G06F17/50
CPC分类号： G06F17/50 , G06F17/5081 , Y02T10/82
摘要： A process and apparatus are provided for automated pattern-based semiconductor design layout correction. Embodiments include scanning a drawn semiconductor design layout to determine a difficult-to-manufacture pattern within the drawn semiconductor design layout based on a match with a pre-characterized difficult-to-manufacture pattern, determining a corrected pattern based on a pre-determined correlation between the corrected pattern and the pre-characterized difficult-to-manufacture pattern, and replacing the difficult-to-manufacture pattern with the corrected pattern within the drawn semiconductor design layout.
摘要翻译：提供了一种用于基于自动图案的半导体设计布局校正的工艺和装置。实施例包括扫描绘制的半导体设计布局以基于与预先表征的难以制造的图案的匹配来确定所绘制的半导体设计布局内的难以制造的图案，基于预定的相关性来确定校正的图案在校正图案和预先表征的难以制造图案之间，并且在所绘制的半导体设计布局内用修正图案代替难以制造的图案。

5. 发明授权

US08418105B1 Methods for pattern matching in a double patterning technology-compliant physical design flow 有权
标题翻译：双图案技术兼容物理设计流程中模式匹配的方法
公开(公告)号：US08418105B1
公开(公告)日：2013-04-09
申请号：US13349412
申请日：2012-01-12
申请人： Lynn T. Wang , Vito Dai , Luigi Capodieci
发明人： Lynn T. Wang , Vito Dai , Luigi Capodieci
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method for fabricating an integrated circuit is disclosed that includes, in accordance with an embodiment, providing a drawn layout logical design for the integrated circuit, the logical design including a plurality of patterns; checking the plurality of patterns for double patterning technology compliance; identifying a non-double patterning technology compliant pattern; providing a double patterning technology compliant pattern for replacing the identified non-double patterning technology compliant pattern, thereby creating a modified logical design; generating a mask set implementing the modified logical design; and employing the mask set to implement the modified logical design in and on a semiconductor substrate.
摘要翻译：公开了一种用于制造集成电路的方法，其包括根据实施例，为集成电路提供绘制的布局逻辑设计，所述逻辑设计包括多个图案; 检查多种图案以进行双重图案化技术合规; 识别非双重图案化技术兼容图案; 提供用于替换所识别的非双图案化技术兼容图案的双重图案化技术兼容图案，由此创建经修改的逻辑设计; 生成实现修改后的逻辑设计的掩码集; 并且采用该掩模组来实现在半导体衬底中和之上的修改的逻辑设计。

6. 发明申请

US20140215415A1 AUTOMATED DESIGN LAYOUT PATTERN CORRECTION BASED ON CONTEXT-AWARE PATTERNS 有权
标题翻译：基于背景图案的自动设计布局图案校正
公开(公告)号：US20140215415A1
公开(公告)日：2014-07-31
申请号：US13755374
申请日：2013-01-31
申请人： Lynn WANG , Vito Dai , Luigi Capodieci
发明人： Lynn WANG , Vito Dai , Luigi Capodieci
IPC分类号： G06F17/50
CPC分类号： G06F17/50 , G06F17/5081 , Y02T10/82
摘要： A process and apparatus are provided for automated pattern-based semiconductor design layout correction. Embodiments include scanning a drawn semiconductor design layout to determine a difficult-to-manufacture pattern within the drawn semiconductor design layout based on a match with a pre-characterized difficult-to-manufacture pattern, determining a corrected pattern based on a pre-determined correlation between the corrected pattern and the pre-characterized difficult-to-manufacture pattern, and replacing the difficult-to-manufacture pattern with the corrected pattern within the drawn semiconductor design layout.
摘要翻译：提供了一种用于基于自动图案的半导体设计布局校正的工艺和装置。实施例包括扫描绘制的半导体设计布局以基于与预先表征的难以制造的图案的匹配来确定所绘制的半导体设计布局内的难以制造的图案，基于预定的相关性来确定校正的图案在校正图案和预先表征的难以制造图案之间，并且在所绘制的半导体设计布局内用修正图案代替难以制造的图案。

7. 发明授权

US07757190B2 Design rules checking augmented with pattern matching 失效
标题翻译：设计规则检查用模式匹配增强
公开(公告)号：US07757190B2
公开(公告)日：2010-07-13
申请号：US11613006
申请日：2006-12-19
申请人： Vito Dai , Jie Yang , Norma Rodriguez , Luigi Capodieci
发明人： Vito Dai , Jie Yang , Norma Rodriguez , Luigi Capodieci
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： Layout patterns are identified as problematic when they have particular parameters required to exceed standard limits. The problematic layout patterns are associated with preferred design rules in a DRC-Plus deck. Layout data is scanned to generate match locations of any problematic layout patterns. The match locations are forwarded to a DRC engine that compares layout parameters of the match locations to corresponding preferred layout rules in the DRC-Plus deck. The DRC-Plus check results are used to modify the layout to improve manufacturability of the layout.
摘要翻译：当他们具有超过标准限制所需的特定参数时，布局模式被识别为有问题的。有问题的布局模式与DRC-Plus面板中的首选设计规则相关联。扫描布局数据以生成任何有问题的布局模式的匹配位置。匹配位置被转发到DRC引擎，其将匹配位置的布局参数与DRC-Plus卡板中的相应优选布局规则进行比较。 DRC-Plus检查结果用于修改布局以提高布局的可制造性。

8. 发明申请

US20080148211A1 Design Rules Checking Augmented With Pattern Matching 失效
标题翻译：通过模式匹配增强设计规则
公开(公告)号：US20080148211A1
公开(公告)日：2008-06-19
申请号：US11613006
申请日：2006-12-19
申请人： Vito Dai , Jie Yang , Norma Rodriguez , Luigi Capodieci
发明人： Vito Dai , Jie Yang , Norma Rodriguez , Luigi Capodieci
IPC分类号： G06F9/455
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： Layout patterns are identified as problematic when they have particular parameters required to exceed standard limits. The problematic layout patterns are associated with preferred design rules in a DRC-Plus deck. Layout data is scanned to generate match locations of any problematic layout patterns. The match locations are forwarded to a DRC engine that compares layout parameters of the match locations to corresponding preferred layout rules in the DRC-Plus deck. The DRC-Plus check results are used to modify the layout to improve manufacturability of the layout.
摘要翻译：当他们具有超过标准限制所需的特定参数时，布局模式被识别为有问题的。有问题的布局模式与DRC-Plus面板中的首选设计规则相关联。扫描布局数据以生成任何有问题的布局模式的匹配位置。匹配位置被转发到DRC引擎，其将匹配位置的布局参数与DRC-Plus卡板中的相应优选布局规则进行比较。 DRC-Plus检查结果用于修改布局以提高布局的可制造性。

9. 发明授权

US09012270B2 Metal layer enabling directed self-assembly semiconductor layout designs 有权
标题翻译：金属层可实现定向自组装半导体布局设计
公开(公告)号：US09012270B2
公开(公告)日：2015-04-21
申请号：US13832442
申请日：2013-03-15
申请人： Ji Xu , Vito Dai
发明人： Ji Xu , Vito Dai
IPC分类号： H01L27/02 , H01L21/768 , H01L23/535
CPC分类号： H01L21/76895 , H01L21/76816 , H01L23/535 , H01L27/0207 , H01L27/092 , H01L2924/0002 , H01L2924/00
摘要： Methods for forming a DSA pre-patterned semiconductor transistor layout and the resulting devices are disclosed. Embodiments may include forming a pre-patterned transistor layout by directed self-assembly (DSA), forming a metal layer over the DSA pre-patterned transistor layout, including: forming a plurality of horizontal metal lines; and forming a plurality of vertical metal segments discontinuous from and between adjacent horizontal metal lines; and forming one or more bridging dots each connecting one of the plurality of horizontal metal lines to one of the plurality of vertical metal segments, wherein locations of the bridging dots determine logic functions of resulting transistor cells.
摘要翻译：公开了形成DSA预图案化半导体晶体管布局的方法和所得到的器件。实施例可以包括通过定向自组装（DSA）形成预先图案化的晶体管布局，在DSA预构图晶体管布局上形成金属层，包括：形成多个水平金属线; 以及形成从相邻的水平金属线之间和之间不连续的多个垂直金属段; 以及形成一个或多个桥接点，每个桥接点将所述多个水平金属线中的一个连接到所述多个垂直金属段中的一个，其中所述桥接点的位置确定所得晶体管单元的逻辑功能。

10. 发明申请

US20130219347A1 METHODS FOR DECOMPOSING CIRCUIT DESIGN LAYOUTS AND FOR FABRICATING SEMICONDUCTOR DEVICES USING DECOMPOSED PATTERNS 有权
标题翻译：用于分解电路设计层和使用分解图案制作半导体器件的方法
公开(公告)号：US20130219347A1
公开(公告)日：2013-08-22
申请号：US13400445
申请日：2012-02-20
申请人： Yi Zou , Swamy Muddu , Lynn T. Wang , Vito Dai , Luigi Capodieci , Peng Xie
发明人： Yi Zou , Swamy Muddu , Lynn T. Wang , Vito Dai , Luigi Capodieci , Peng Xie
IPC分类号： G06F17/50
CPC分类号： G03F1/70
摘要： Methods for fabricating semiconductor devices are provided. In an embodiment, a method of fabricating a semiconductor device includes scanning a circuit design layout and proposing patterns for decomposed layouts. The proposed patterns are then compared with a library of prior patterns including a category of forbidden patterns and a category of preferred patterns. If a selected proposed pattern matches a forbidden pattern, the selected proposed pattern is eliminated. If the selected proposed pattern matches a preferred pattern, then the selected proposed pattern is identified for use in the decomposed layouts. Decomposed layouts are generated from the identified patterns. A plurality of masks is fabricated based on the decomposed layouts. Then a multiple patterning lithographic technique is performed with the plurality of masks on a semiconductor substrate.
摘要翻译：提供制造半导体器件的方法。在一个实施例中，制造半导体器件的方法包括扫描电路设计布局并提出用于分解布局的图案。然后将所提出的模式与包括禁止模式类别和优选模式类别的先前模式的库进行比较。如果所选择的提议模式匹配禁止模式，则删除所选择的提议模式。如果所选择的提出的模式匹配优选模式，则所选择的提出的模式被识别用于分解的布局。分辨的布局是从识别的图案生成的。基于分解的布局制造多个掩模。然后用半导体衬底上的多个掩模进行多重图形化光刻技术。

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