专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20170054013A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20170054013A1
公开(公告)日：2017-02-23
申请号：US15230557
申请日：2016-08-08
申请人： Kabushiki Kaisha Toshiba
发明人： Keiichi MATSUSHITA
IPC分类号： H01L29/778 , H01L23/31 , H01L29/20
CPC分类号： H01L23/3171 , H01L29/2003 , H01L29/432 , H01L29/7786
摘要： A semiconductor device includes a substrate; a first nitride semiconductor layer formed on the substrate, a second nitride semiconductor layer formed on the first nitride semiconductor layer and containing gallium element; and a third nitride semiconductor layer formed on the second nitride semiconductor layer and containing indium element, aluminum element, and gallium element, in which the composition ratio of the gallium element of the third nitride semiconductor layer is a proportion smaller than that of the second nitride semiconductor layer.
摘要翻译：半导体器件包括衬底; 形成在所述基板上的第一氮化物半导体层，形成在所述第一氮化物半导体层上并含有镓元素的第二氮化物半导体层; 以及形成在所述第二氮化物半导体层上并且包含铟元素，铝元素和镓元素的第三氮化物半导体层，其中所述第三氮化物半导体层的所述镓元素的组成比例小于所述第二氮化物半导体层的比例半导体层。

2. 发明申请

US20190198655A1 SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：US20190198655A1
公开(公告)日：2019-06-27
申请号：US16021984
申请日：2018-06-28
申请人： Kabushiki Kaisha Toshiba , Toshiba Infrastructure Systems & Solutions Corporation
发明人： Keiichi MATSUSHITA
IPC分类号： H01L29/778 , H01L29/20 , H01L29/205 , H01L29/417 , H01L23/31 , H01L21/02 , H01L21/306 , H01L21/24 , H01L29/66
CPC分类号： H01L29/7787 , H01L21/0217 , H01L21/02274 , H01L21/0254 , H01L21/0262 , H01L21/246 , H01L21/30621 , H01L23/3171 , H01L29/2003 , H01L29/205 , H01L29/41766 , H01L29/66462
摘要： A semiconductor device includes a substrate: a first nitride semiconductor layer formed on the substrate; a second nitride semiconductor layer formed on the first nitride semiconductor layer and containing a gallium element; a source electrode and a drain electrode formed on the second nitride semiconductor layer and contacting the second nitride semiconductor layer; a third nitride semiconductor layer formed on the second nitride semiconductor layer and containing an indium element and an aluminum element; and a gate electrode formed on the third nitride semiconductor layer and formed between the source electrode and the drain electrode.

3. 发明申请

US20170256626A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：US20170256626A1
公开(公告)日：2017-09-07
申请号：US15299572
申请日：2016-10-21
申请人： Kabushiki Kaisha Toshiba
发明人： Keiichi MATSUSHITA
IPC分类号： H01L29/51 , H01L21/324 , H01L21/02 , H01L29/20 , H01L29/36
CPC分类号： H01L21/324 , H01L21/0217 , H01L21/02274 , H01L23/291 , H01L23/3171 , H01L29/2003 , H01L29/42316 , H01L29/66462 , H01L29/7786
摘要： A semiconductor device includes a substrate, a nitride semiconductor layer formed on the substrate, a gate electrode formed on the nitride semiconductor layer; and a silicon nitride layer which coats the gate electrode and is formed on the nitride semiconductor layer, wherein the silicon nitride layer has a refractive index of less than 1.9 at the nitride semiconductor layer side.

4. 发明申请

US20180277650A1 SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：US20180277650A1
公开(公告)日：2018-09-27
申请号：US15877815
申请日：2018-01-23
申请人： Kabushiki Kaisha Toshiba , Toshiba Infrastructure Systems & Solutions Corporation
发明人： Keiichi MATSUSHITA
IPC分类号： H01L29/66 , H01L29/417 , H01L29/423 , H01L29/20 , H01L29/205 , H01L29/49 , H01L29/51 , H01L21/28 , H01L29/778 , H01L21/02 , H01L21/311
CPC分类号： H01L29/66462 , H01L21/0217 , H01L21/02211 , H01L21/02274 , H01L21/02378 , H01L21/0254 , H01L21/0262 , H01L21/28264 , H01L21/31111 , H01L21/31144 , H01L23/291 , H01L29/2003 , H01L29/205 , H01L29/41775 , H01L29/42316 , H01L29/42368 , H01L29/42376 , H01L29/4238 , H01L29/4983 , H01L29/518 , H01L29/7786 , H01L29/7787
摘要： A semiconductor device includes a semiconductor layer provided on a substrate, a drain electrode and a source electrode provided on the semiconductor layer, and a gate electrode provided on the semiconductor layer such that an angle between a lateral surface and the semiconductor layer gradually decreases toward the semiconductor layer.

5. 发明申请

US20150279924A1 MIM CAPACITOR AND METHOD OF MANUFACTURING MIM CAPACITOR 审中-公开
标题翻译： MIM电容器及制造MIM电容器的方法
公开(公告)号：US20150279924A1
公开(公告)日：2015-10-01
申请号：US14669283
申请日：2015-03-26
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Keiichi MATSUSHITA
IPC分类号： H01L49/02 , H01L23/00
CPC分类号： H01L28/65 , H01L23/5221 , H01L23/5223 , H01L24/43 , H01L24/45 , H01L28/60 , H01L2224/45144 , H01L2924/01022 , H01L2924/01078 , H01L2924/01079 , H01L2924/206
摘要： An MIM capacitor includes a lower electrode on a surface of a semiconductor substrate, an insulating film on the surface of the semiconductor substrate and a portion of the lower electrode, an upper electrode on a surface of a portion of the insulating film above the lower electrode, and an air bridge wire connected only to a central region of a surface of the upper electrode so as to be spaced above an end region of the surface of the upper electrode.
摘要翻译： MIM电容器包括在半导体衬底的表面上的下电极，半导体衬底的表面上的绝缘膜和下电极的一部分，在下电极上方的绝缘膜的一部分的表面上的上电极以及空气桥线，其仅与上部电极的表面的中心区域连接，以在上部电极的表面的端部区域的上方间隔开。

6. 发明申请

US20160071939A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20160071939A1
公开(公告)日：2016-03-10
申请号：US14792107
申请日：2015-07-06
申请人： Kabushiki Kaisha Toshiba
发明人： Keiichi MATSUSHITA
IPC分类号： H01L29/417 , H01L29/06 , H01L29/778
CPC分类号： H01L29/41766 , H01L29/2003 , H01L29/66462 , H01L29/7786
摘要： A semiconductor device includes a substrate, a semiconductor layer having a buffer layer, a spacer layer, and barrier layer sequentially stacked on the substrate, and first and second ohmic electrodes installed on an upper surface of the barrier layer in the substrate to be separated from each other. Each of the first and second ohmic electrodes includes a portion formed on the upper surface of the barrier layer and electrode portions filling a plurality of grooves penetrating from the upper surface of the barrier layer through the barrier layer and the spacer layer and reaching a region of a two-dimensional electron gas layer formed in a spacer-layer side of the buffer layer, the electrode portions being in contact with side walls of each of the plurality of the grooves, and the portion formed on the upper surface of the barrier layer and the electrode portions are integrally formed.
摘要翻译：半导体器件包括基板，具有缓冲层的半导体层，顺序地层叠在基板上的隔离层和阻挡层，以及安装在基板中的阻挡层的上表面上以分离的第一和第二欧姆电极彼此。第一和第二欧姆电极中的每一个包括形成在阻挡层的上表面上的部分，以及电极部分，其填充通过阻挡层和间隔层从阻挡层的上表面穿透的多个槽，并且到达形成在缓冲层的间隔层侧的二维电子气层，电极部分与多个沟槽中的每一个的侧壁接触，形成在阻挡层的上表面上的部分和电极部一体形成。

7. 发明申请

US20150069597A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20150069597A1
公开(公告)日：2015-03-12
申请号：US14322216
申请日：2014-07-02
申请人： Kabushiki Kaisha Toshiba
发明人： Keiichi MATSUSHITA , Yo SASAKI
IPC分类号： H01L23/373 , H01L23/00
CPC分类号： H01L23/3736 , H01L21/50 , H01L23/10 , H01L23/142 , H01L23/4827 , H01L24/03 , H01L24/05 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/83 , H01L2224/0346 , H01L2224/04026 , H01L2224/05073 , H01L2224/05082 , H01L2224/05083 , H01L2224/05144 , H01L2224/05155 , H01L2224/05164 , H01L2224/05166 , H01L2224/05169 , H01L2224/05647 , H01L2224/2741 , H01L2224/2743 , H01L2224/29082 , H01L2224/29083 , H01L2224/29084 , H01L2224/29111 , H01L2224/29144 , H01L2224/29147 , H01L2224/29155 , H01L2224/29164 , H01L2224/29166 , H01L2224/29169 , H01L2224/32245 , H01L2224/32501 , H01L2224/48091 , H01L2224/73265 , H01L2224/83192 , H01L2224/83193 , H01L2224/83203 , H01L2224/83359 , H01L2224/83379 , H01L2224/83447 , H01L2224/83825 , H01L2224/85444 , H01L2924/00014 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01046 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/10272 , H01L2924/10329 , H01L2924/1033 , H01L2924/13064 , H01L2924/13091 , H01L2924/161 , H01L2924/16195 , H01L2924/163 , H01L2924/171 , H01L2924/2064 , H01L2224/05644 , H01L2924/00012 , H01L2224/06164 , H01L2224/45099
摘要： According to one embodiment, a semiconductor device includes a semiconductor element, a mounting member including Cu, and a bonding layer provided between the semiconductor element and the mounting member. The bonding layer includes a first region including Ti and Cu, and a second region provided between the first region and the mounting member, and including Sn and Cu. A first position along the first direction is positioned between the semiconductor element and a second position along the first direction. The first position is where the composition ratio of Ti in the first region is 0.1 times a maximum value of the composition ratio of Ti. The second position is where the composition ratio of Sn in the second region is 0.1 times a maximum value of the composition ratio of Sn. A distance between the first position and the second position is not less than 0.1 micrometers.
摘要翻译：根据一个实施例，半导体器件包括半导体元件，包括Cu的安装构件和设置在半导体元件和安装构件之间的接合层。接合层包括包括Ti和Cu的第一区域，以及设置在第一区域和安装构件之间的包括Sn和Cu的第二区域。沿着第一方向的第一位置位于半导体元件和沿第一方向的第二位置之间。第一位置是第一区域中的Ti的组成比为Ti的组成比的最大值的0.1倍。第二位置是第二区域中的Sn的组成比为Sn的组成比的最大值的0.1倍。第一位置和第二位置之间的距离不小于0.1微米。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式