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1. 发明申请

US20120042116A1 MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME 有权
标题翻译：包括其的存储器件和存储器系统
公开(公告)号：US20120042116A1
公开(公告)日：2012-02-16
申请号：US13210591
申请日：2011-08-16
申请人： KYU-MIN PARK , Byoung-Sul Kim , Hak-Yong Lee , Jun-Ho Jo
发明人： KYU-MIN PARK , Byoung-Sul Kim , Hak-Yong Lee , Jun-Ho Jo
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G06F13/4086
摘要： A memory device includes an interface unit and a memory unit. The interface unit receives a clock signal, a command signal and a data signal, internally adjusts input impedance based upon at least one of the command signal and the clock signal, and generates internal control signal of the memory device based upon the command signal and data signal. The memory unit performs read/write operations based upon the internal control signal.
摘要翻译：存储装置包括接口单元和存储单元。接口单元接收时钟信号，命令信号和数据信号，根据命令信号和时钟信号中的至少一个在内部调整输入阻抗，并根据命令信号和数据产生存储器件的内部控制信号信号。存储单元基于内部控制信号执行读/写操作。

2. 发明授权

US09218312B2 Memory device and memory system including the same 有权
标题翻译：存储器件和存储器系统包括相同的
公开(公告)号：US09218312B2
公开(公告)日：2015-12-22
申请号：US13210591
申请日：2011-08-16
申请人： Kyu-Min Park , Byoung-Sul Kim , Hak-Yong Lee , Jun-Ho Jo
发明人： Kyu-Min Park , Byoung-Sul Kim , Hak-Yong Lee , Jun-Ho Jo
IPC分类号： G06F12/00 , G06F13/40
CPC分类号： G06F13/4086
摘要： A memory device includes an interface unit and a memory unit. The interface unit receives a clock signal, a command signal and a data signal, internally adjusts input impedance based upon at least one of the command signal and the clock signal, and generates internal control signal of the memory device based upon the command signal and data signal. The memory unit performs read/write operations based upon the internal control signal.
摘要翻译：存储装置包括接口单元和存储单元。接口单元接收时钟信号，命令信号和数据信号，根据命令信号和时钟信号中的至少一个在内部调整输入阻抗，并根据命令信号和数据产生存储器件的内部控制信号信号。存储单元基于内部控制信号执行读/写操作。

3. 发明授权

US08618540B2 Semiconductor packages 有权
标题翻译：半导体封装
公开(公告)号：US08618540B2
公开(公告)日：2013-12-31
申请号：US13118948
申请日：2011-05-31
申请人： Jun-Ho Jo , Byoung-Sul Kim , Kwang-Won Park , Hak-Yong Lee
发明人： Jun-Ho Jo , Byoung-Sul Kim , Kwang-Won Park , Hak-Yong Lee
IPC分类号： H01L23/58
CPC分类号： G11C5/02 , H01L23/49816 , H01L23/49838 , H01L2924/0002 , H01L2924/00
摘要： Provided are a semiconductor package, a semiconductor memory module including the semiconductor package, and a system including the semiconductor memory module. The semiconductor package may include a plurality of main terminals arranged on a surface of the semiconductor package with constant intervals, and the plurality of main terminals may include terminals of a first set including a plurality of input/output terminals to which test signals may be input, and terminals of a second set including a plurality of input/output terminals to/from which signals other than the test signals may be input/output.
摘要翻译：提供半导体封装，包括半导体封装的半导体存储器模块和包括半导体存储器模块的系统。半导体封装可以包括以恒定间隔布置在半导体封装的表面上的多个主端子，并且多个主端子可以包括包括可以输入测试信号的多个输入/输出端子的第一组的端子，以及可以输入/输出除了测试信号之外的信号的多个输入/输出端子的第二组的端子。

4. 发明申请

US20080175081A1 Semiconductor memory device and operation control method thereof 有权
标题翻译：半导体存储器件及其操作控制方法
公开(公告)号：US20080175081A1
公开(公告)日：2008-07-24
申请号：US12007518
申请日：2008-01-11
申请人： Byoung-Sul Kim , Joon Hee Lee , Jae In Song , Jun-Ho Jo
发明人： Byoung-Sul Kim , Joon Hee Lee , Jae In Song , Jun-Ho Jo
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C11/4094 , G11C7/1042 , G11C11/4076
摘要： A semiconductor memory device and an operation control method thereof are provided. The method may comprise executing a control such that a precharge operating mode and an active operating mode may be successively performed in response to one pre-active command, thereby reducing the current consumption and loading of the system, and thus, enhancing system performance.
摘要翻译：提供半导体存储器件及其操作控制方法。该方法可以包括执行控制，使得响应于一个预先活动命令可以连续执行预充电操作模式和主动操作模式，从而减少系统的电流消耗和负载，从而提高系统性能。

5. 发明授权

US07782693B2 Semiconductor memory device and operation control method thereof 有权
标题翻译：半导体存储器件及其操作控制方法
公开(公告)号：US07782693B2
公开(公告)日：2010-08-24
申请号：US12007518
申请日：2008-01-11
申请人： Byoung-Sul Kim , Joon-Hee Lee , Jae-in Song , Jun-Ho Jo
发明人： Byoung-Sul Kim , Joon-Hee Lee , Jae-in Song , Jun-Ho Jo
IPC分类号： G11C7/00
CPC分类号： G11C11/4094 , G11C7/1042 , G11C11/4076
摘要： A semiconductor memory device and an operation control method thereof are provided. The method may comprise executing a control such that a precharge operating mode and an active operating mode may be successively performed in response to one pre-active command, thereby reducing the current consumption and loading of the system, and thus, enhancing system performance.
摘要翻译：提供半导体存储器件及其操作控制方法。该方法可以包括执行控制，使得响应于一个预先活动命令可以连续执行预充电操作模式和主动操作模式，从而减少系统的电流消耗和负载，从而提高系统性能。

6. 发明授权

US07154791B2 Redundancy circuit 有权
标题翻译：冗余电路
公开(公告)号：US07154791B2
公开(公告)日：2006-12-26
申请号：US10867491
申请日：2004-06-14
申请人： Byoung-Sul Kim
发明人： Byoung-Sul Kim
IPC分类号： G11C7/00
CPC分类号： G11C29/812 , G11C29/787
摘要： A redundancy circuit for use with a semiconductor memory device is provided. The redundancy circuit includes input address buffers for storing input address bits; fuse boxes for storing repair address bits; a comparator for comparing the input address bits stored in the input address buffers with the repair address bits stored in the fuse boxes; and a redundancy enable determiner for determining whether a redundant memory cell is to be applied to the memory device according to a comparison result of the comparator.
摘要翻译：提供了一种与半导体存储器件一起使用的冗余电路。冗余电路包括用于存储输入地址位的输入地址缓冲器; 用于存储修复地址位的保险丝盒; 用于将存储在输入地址缓冲器中的输入地址位与存储在保险丝盒中的修复地址位进行比较的比较器; 以及冗余使能确定器，用于根据比较器的比较结果确定是否将冗余存储器单元应用于存储器件。

7. 发明申请

US20050041492A1 Redundancy circuit 有权
标题翻译：冗余电路
公开(公告)号：US20050041492A1
公开(公告)日：2005-02-24
申请号：US10867491
申请日：2004-06-14
申请人： Byoung-Sul Kim
发明人： Byoung-Sul Kim
IPC分类号： G11C7/00 , G11C29/00
CPC分类号： G11C29/812 , G11C29/787
摘要： A redundancy circuit for use with a semiconductor memory device is provided. The redundancy circuit includes input address buffers for storing input address bits; fuse boxes for storing repair address bits; a comparator for comparing the input address bits stored in the input address buffers with the repair address bits stored in the fuse boxes; and a redundancy enable determiner for determining whether a redundant memory cell is to be applied to the memory device according to a comparison result of the comparator.
摘要翻译：提供了一种与半导体存储器件一起使用的冗余电路。冗余电路包括用于存储输入地址位的输入地址缓冲器; 用于存储修复地址位的保险丝盒; 用于将存储在输入地址缓冲器中的输入地址位与存储在保险丝盒中的修复地址位进行比较的比较器; 以及冗余使能确定器，用于根据比较器的比较结果确定是否将冗余存储器单元应用于存储器件。

8. 发明申请

US20130067145A1 MEMORY DEVICE, MEMORY SYSTEM, AND METHOD OF STORING DATA USING THE SAME 审中-公开
标题翻译：存储器件，存储器系统以及使用其存储数据的方法
公开(公告)号：US20130067145A1
公开(公告)日：2013-03-14
申请号：US13592717
申请日：2012-08-23
申请人： Byoung-Sul Kim , Myong-Jae Kim , Woo-Il Kim
发明人： Byoung-Sul Kim , Myong-Jae Kim , Woo-Il Kim
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F2212/7201 , G06F2212/7208 , G06F2212/7209
摘要： Provided is a memory device configured to store data having a first characteristic and a second characteristic in a memory region optimized to store data having the first characteristic and the second characteristic. The memory device includes a plurality of memory regions and a region determination unit configured to receive data, select a memory region appropriate for storing the received data, and store the data in the selected memory region. Correspondingly, performance degradation of the memory device may be prevented.
摘要翻译：提供了一种存储器件，其被配置为将存储区域中具有第一特征和第二特性的数据存储在优化以存储具有第一特性和第二特性的数据的存储区域中。存储装置包括多个存储区域和区域确定单元，被配置为接收数据，选择适于存储接收到的数据的存储区域，并将数据存储在所选存储区域中。相应地，可以防止存储器件的性能下降。

9. 发明授权

US08108741B2 Semiconductor memory device having mount test circuits and mount test method thereof 失效
标题翻译：具有安装测试电路及其安装测试方法的半导体存储器件
公开(公告)号：US08108741B2
公开(公告)日：2012-01-31
申请号：US12219815
申请日：2008-07-29
申请人： Byoung-Sul Kim , Joon-Hee Lee , Kwan-Yong Jin , Seung-Hee Lee
发明人： Byoung-Sul Kim , Joon-Hee Lee , Kwan-Yong Jin , Seung-Hee Lee
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/28 , G11C29/40 , G11C2029/4002
摘要： A semiconductor memory device having a mount test circuit and a mount test method thereof are provided. The test circuit for use in a semiconductor memory device including a plurality of memory blocks may include a comparison unit for comparing test data of at least two memory blocks selected from the plurality of memory blocks, deciding whether or not the test data of the selected memory blocks are identical, and outputting a pass signal or fail signal as a flag signal; and an output selection unit for selecting any one of the selected memory blocks as an output memory block, and changing the output memory block whenever the fail signal is generated from the comparison unit, thus forming it as a data output path, which may lessen error occurrence.
摘要翻译：提供一种具有安装测试电路及其安装测试方法的半导体存储器件。用于包括多个存储块的半导体存储器件的测试电路可以包括：比较单元，用于比较从多个存储块中选出的至少两个存储块的测试数据，判断所选择的存储器的测试数据块相同，并输出通过信号或失败信号作为标志信号; 以及输出选择单元，用于选择所选择的存储器块中的任何一个作为输出存储器块，并且每当从比较单元产生故障信号时改变输出存储器块，从而将其形成为可以减少误差的数据输出路径发生。

10. 发明授权

US07206237B2 Apparatus and method for testing a memory device with multiple address generators 失效
标题翻译：用于测试具有多个地址发生器的存储器件的装置和方法
公开(公告)号：US07206237B2
公开(公告)日：2007-04-17
申请号：US11118223
申请日：2005-04-28
申请人： Byoung-Sul Kim
发明人： Byoung-Sul Kim
IPC分类号： G11C7/00
CPC分类号： G11C29/44 , G11C2029/0405 , G11C2029/1208 , G11C2029/1806
摘要： An apparatus includes a test signal path to provide a test signal to a memory cell array responsive to an address generating command, the test signal to access a memory cell within the memory cell array, a failure address path to generate a failure address responsive to the address generating command, and a failure discriminator to determine a result responsive to the access, the result to indicate whether the memory cell is faulty, and to store the result according to the failure address.
摘要翻译：一种装置包括测试信号路径，用于响应于地址产生命令向存储器单元阵列提供测试信号，该测试信号访问存储单元阵列内的存储单元，故障地址路径以响应于该故障地址产生故障地址地址产生命令，以及故障鉴别器，用于确定响应于该访问的结果，指示存储器单元是否有故障的结果，以及根据故障地址存储结果。

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