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    • 2. 发明申请
    • A SEMICONDUCTOR DEVICE HAVING A RECESS WITH NON-POROUS WALLS IN A POROUS DIELECTRIC AND A METHOD OF MANUFACTURING SUCH A SEMICONDUCTOR DEVICE
    • 具有多孔电介质中的非多孔性凹坑的半导体器件和制造这种半导体器件的方法
    • WO2006064416A1
    • 2006-06-22
    • PCT/IB2005/054101
    • 2005-12-07
    • KONINKLIJKE PHILIPS ELECTRONICS N.V.FURUKAWA, YukikoMACNEIL, John
    • FURUKAWA, YukikoMACNEIL, John
    • H01L21/768
    • H01L21/76814H01L21/7682H01L21/76826H01L21/76831H01L2221/1047
    • This invention relates to a semiconductor device and a method of manufacturing such a device. An embodiment of the semiconductor device (1) according to the invention comprises a substrate (10), a dielectric layer (21) applied to the substrate (10), the dielectric layer (21) having a recess (50), the recess (50) having walls defined by the dielectric layer (21), the recess (50) being filled with a conductor (90), the conductor (90) being embedded by a barrier layer (85) at least on sidewalls of the conductor (90), while the dielectric layer (21) comprises non-porous regions (75) adjacent to the walls of the recess (50) and porous regions (25) away from the recess (50). The conductor (90) is provided with a capping layer (95). It is an important aspect of the invention that the width W of the non- porous regions (75) is smaller than 40 nanometer. The smaller the width of the modified regions the lower the effective k- value. A further important aspect of the invention is that the modified layers 75 are substantially free of silicon oxide like material.
    • 本发明涉及一种半导体器件及其制造方法。 根据本发明的半导体器件(1)的实施例包括衬底(10),施加到衬底(10)的电介质层(21),电介质层(21)具有凹部(50),凹部 50)具有由介电层(21)限定的壁,凹部(50)填充有导体(90),导体(90)至少在导体(90)的侧壁上被阻挡层(85)嵌入 ),而电介质层(21)包括与凹部(50)的壁相邻的非多孔区域(75)和远离凹部(50)的多孔区域(25)。 导体(90)设置有覆盖层(95)。 本发明的一个重要方面是,非多孔区域(75)的宽度W小于40纳米。 修改区域的宽度越小,有效k值越低。 本发明的另一重要方面是改性层75基本上不含氧化硅类材料。