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1. 发明授权

US3895978A Method of manufacturing transistors 失效
标题翻译：制造晶体管的方法
公开(公告)号：US3895978A
公开(公告)日：1975-07-22
申请号：US16020171
申请日：1971-07-06
申请人： KOGYO GIJUTSUIN
发明人： TARUI YASUO , HAYASHI YUTAKA , SEKIGAWA TOSHIHIRO
IPC分类号： H01L21/00 , H01L21/8234 , H01L27/00 , H01L27/088 , H01L29/00 , H01L29/06 , H01L29/10 , H01L29/423 , H01L29/45 , H01L29/78 , H01L7/44
CPC分类号： H01L29/7816 , H01L21/00 , H01L21/8234 , H01L27/00 , H01L27/088 , H01L29/00 , H01L29/0696 , H01L29/1045 , H01L29/42368 , H01L29/42376 , H01L29/456 , H01L29/7801 , H01L29/7802 , H01L29/7839
摘要： Improved field-effect transistors, in which effective base width is determined by impurity diffusion length or by difference between impurity diffusion lengths capable of reducing parasitic capacitance between gate and drain and or between gate or drain and other electrode, construction capable of leading out simply and effectively electrode from the base region and or source region, and methods adapted to manufacture the above-mentioned field-effect transistors and lateral transistors are disclosed herein.
摘要翻译：改进的场效应晶体管，其中有效基极宽度由杂质扩散长度或能够减小栅极和漏极之间和/或栅极或漏极与其它电极之间的寄生电容的杂质扩散长度之间的差异决定，能够简单地导出本文公开了适用于制造上述场效应晶体管和横向晶体管的方法，从基极区域和/或源极区域有效地进行电极的制造。

2. 发明授权

US3923553A Method of manufacturing lateral or field-effect transistors 失效
标题翻译：制造横向或场效晶体管的方法
公开(公告)号：US3923553A
公开(公告)日：1975-12-02
申请号：US42288173
申请日：1973-12-07
申请人： KOGYO GIJUTSUIN
发明人： HAYASHI YUTAKA , TARUI YASUO
IPC分类号： H01L21/00 , H01L21/761 , H01L21/8248 , H01L21/8249 , H01L27/00 , H01L27/06 , H01L29/78 , H01L7/44
CPC分类号： H01L29/7816 , H01L21/00 , H01L21/761 , H01L21/8248 , H01L21/8249 , H01L27/00 , H01L27/0623 , H01L29/7801 , Y10T29/5178
摘要： In a field-effect transistor (hereinafter referred to as FET) and a lateral transistor in which its effective base width is determined by diffusion distances of impurities or a difference of diffusion distances due to impurities, a base region is made to be continuous with a region formed by another process step and having an impurity of the same conductivity type as that of the base region, or is overlapped by a region having an impurity of opposite conductivity type to that of the base region. Furthermore, modifications adapted for integrated circuits of aforementioned FET and methods of manufacturing them are disclosed.
摘要翻译：在场效应晶体管（以下称为FET）和横向晶体管中，其有效基极宽度由杂质的扩散距离或由于杂质导致的扩散距离差确定，使基极区域与通过另一工艺步骤形成并且具有与基极区相同的导电类型的杂质，或者与具有与基极区相反的导电类型杂质的区域重叠。

3. 发明授权

US3919007A Method of manufacturing a field-effect transistor 失效
标题翻译：制造场效应晶体管的方法
公开(公告)号：US3919007A
公开(公告)日：1975-11-11
申请号：US34175673
申请日：1973-03-15
申请人： KOGYO GIJUTSUIN
发明人： TARUI YASUO , HAYASHI YUTAKA , SEKIGAWA TOSHIHIRO
IPC分类号： H01L21/00 , H01L21/223 , H01L21/8234 , H01L27/00 , H01L27/088 , H01L29/00 , H01L29/06 , H01L29/10 , H01L29/423 , H01L29/45 , H01L29/78 , H01L7/44
CPC分类号： H01L29/7816 , H01L21/00 , H01L21/223 , H01L21/8234 , H01L27/00 , H01L27/088 , H01L29/00 , H01L29/0696 , H01L29/1045 , H01L29/42368 , H01L29/42376 , H01L29/456 , H01L29/7801 , H01L29/7802 , H01L29/7839 , Y10S148/106 , Y10S148/145 , Y10S148/151 , Y10S148/167
摘要： The method for making an improved field-effect transistor by using a thick insulating layer, the thickness of which is larger than the diffusion length of the impurity forming the base region in a following process step, as a mask for successive diffusion of two different impurities of different conductivity types and by using a portion of the thick insulating layer on the drain region as a portion of the gate insulating layer to reduce a parastic capacitance between the gate and the drain.
摘要翻译：通过使用其厚度大于后续工艺步骤中形成基极区域的杂质的扩散长度的厚绝缘层来制造改进的场效应晶体管的方法，作为两种不同杂质的连续扩散的掩模的不同导电类型，并且通过使用漏极区上的厚绝缘层的一部分作为栅极绝缘层的一部分，以减小栅极和漏极之间的残余电容。

4. 发明授权

US3690966A Method of manufacturing microstructures 失效
标题翻译：制造微结构的方法
公开(公告)号：US3690966A
公开(公告)日：1972-09-12
申请号：US3690966D
申请日：1970-03-31
申请人： KOGYO GIJUTSUIN
发明人： HAYASHI YUTAKA , TARUI YASUO
IPC分类号： H05K3/46 , C23F1/00 , H01L21/00 , H01L21/22 , H01L21/28 , H01L21/288 , H01L21/306 , H01L21/331 , H01L23/29 , H01L29/73 , H01L29/78 , H01L49/02 , H01L7/44
CPC分类号： H01L23/291 , H01L21/00 , H01L21/288 , H01L23/29 , H01L49/02 , H01L2924/0002 , Y10S148/043 , Y10S148/051 , Y10S148/053 , Y10S148/106 , Y10S438/944 , H01L2924/00
摘要： A METHOD OF MANUFACTURING A MICROSTRUCTURE WHICH COMPRISES FORMING A SUBSTANCE LAYER ON THE SURFACE OF A WORKPIECE, WORKING SAID SUBSTANCE LAYER INTO A DESIRED CONFIGURATION DURING OR AFTER SAID FORMATION THEREOF, CHANGING THE COMPOSITION OF A PORTION OF THE SAID SURFACE LAYER 7, SAID SURFACE LAYER HAVING A HOLE IN THE PORTION OF SAID SURFACE LAYER WHOSE COMPOSITION HAS BEEN CHANGED, REMOVING THE REMAINDER OF SAID SUBSTANCE LAYER PREVIOUSLY FORMED THROUGH SAID HOLE, AND UTILIZING AS A PROCESSING MEANS THE PORTION OF SAID SURFACE LAYER OF CHANGED COMPOSITION, ADJACENT TO SAID WORKPIECE.

5. 发明授权

US3602809A High speed function tester for integrated circuits 失效
标题翻译：用于集成电路的高速功能测试仪
公开(公告)号：US3602809A
公开(公告)日：1971-08-31
申请号：US3602809D
申请日：1969-06-09
申请人： KOGYO GIJUTSUIN
发明人： TARUI YASUO , HAYASHI YUTAKA
IPC分类号： G01R31/319 , G01R27/00
CPC分类号： G01R31/31917
摘要： The test apparatus is composed of a clock signal generating circuit, a patterned pulse generating circuit operated in synchronism with the clock signal generating circuit, with the output of the patterned pulse generating circuit being furnished to an integrated circuit to be tested, a reference voltage generating circuit, a comparator circuit to compare the output pulses from the integrated circuit to be tested with the output from the reference voltage generating circuit, a function pulse generating circuit synchronized with an output from the comparator circuit, a circuit for detecting coincidence between the output from the comparator circuit and the output from the function pulse generating circuit, and a displaying circuit to display the output of the coincidence detecting circuit, whereby the validity of the integrated circuit is determined from the coincidence of the output pulses from the integrated circuit with the expected pulse patterns obtained from the function pulse generating circuit.

6. 发明专利

AU572345B2 THIN FILM FORMING DEVICE 未知
公开(公告)号：AU572345B2
公开(公告)日：1988-05-05
申请号：AU4738385
申请日：1985-09-11
申请人： KOGYO GIJUTSUIN
发明人： HAYASHI YUTAKA , ITOH ATSUO , IIDA HIDEYO
IPC分类号： H01B5/14 , B05B1/14 , C03C17/25 , C23C18/12 , H01B13/00 , H01L21/283 , H01L21/288 , H01L31/042 , B05B13/00 , C03C17/22

7. 发明专利

GB2107519B NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 未知
公开(公告)号：GB2107519B
公开(公告)日：1985-12-18
申请号：GB8229197
申请日：1982-10-13
申请人： KOGYO GIJUTSUIN , SEIKO INSTR & ELECTRONICS
发明人： HAYASHI YUTAKA , KOJIMA YOSHIKAZU , KAMIYA MASAAKI , TANAKA KOJIRO
IPC分类号： H01L27/112 , G11C16/04 , G11C17/00 , H01L21/8246 , H01L21/8247 , H01L29/788 , H01L29/792 , H01L29/78
摘要： In the non-volatile semiconductor memory of present invention, a select gate and a floating gate are formed on the surface portion of the substrate between a source region and the drain region also acting as a control gate through a gate oxide film. A part of a channel current is injected into the floating gate at the surface portion under the edge of the floating gate covered by the select gate.

8. 发明专利

AU534002B2 AMORPHOUS SEMICONDUCTOR SOLAR CELL 未知
公开(公告)号：AU534002B2
公开(公告)日：1983-12-22
申请号：AU8850782
申请日：1982-09-17
申请人： KOGYO GIJUTSUIN , TAIYO YUDEN KK
发明人： HAYASHI YUTAKA , YAMANAKI MITSUYUKI
IPC分类号： H01L31/04 , H01L31/0224 , H01L31/18 , H01L31/02
摘要： An amorphous semiconductor solar cell which comprises a glass substrate and a transparent electrode coated on the substrate. The device also comprises an amorphous semiconductor layer on the transparent electrode, and a rear electrode on the amorphous layer, wherein the average grain diameter of the surface of the transparent electrode ranges from 0.1 mu m to 2.5 mu m.

9. 发明专利

DE3431603C2 未知
公开(公告)号：DE3431603C2
公开(公告)日：1994-07-07
申请号：DE3431603
申请日：1984-08-28
申请人： TAIYO YUDEN KK , KOGYO GIJUTSUIN
发明人： HAYASHI YUTAKA , IIDA HIDEYO , MISHUKU TOSHIO
IPC分类号： H01L31/04 , H01L31/0236 , H01L31/052
摘要： A photoelectric transducer comprising at least a light-transmissive substrate having a relatively flat surface provided on its light-receiving side and an uneven surface provided on its opposite side, and a photoelectric transducing layer provided on the uneven surface of the substrate. The photoelectric transducing layer comprises at least a light-transmissive conductive layer, a semiconductor layer, and a back conductive electrode layer. The back conductive electrode layer comprises a second light-transmissive conductive layer and a conductive layer. The uneven surface on the substrate includes numerous projections, each projection having a triangular section and a shape of pyramidal, ridged roof, or conical type. The projections and the second light-transmissive conductive layer of the uneven back conductive electrode layer elongate the optical path of light beams in the photoelectric transducing layer, and prevent the adherence of dust particles and the abrasion of the photoelectric transducing layer.

10. 发明专利

GB2113002A AMORPHOUS SEMICONDUCTOR SOLAR BATTERY ELECTRODE 未知
公开(公告)号：GB2113002A
公开(公告)日：1983-07-27
申请号：GB8228022
申请日：1982-09-30
申请人： KOGYO GIJUTSUIN , TAIYO YUDEN KK
发明人： HAYASHI YUTAKA , YAMANAKA MITSUYUKI , IIDA HIDEYO , SHIBA NOBUYASU , KARASAWA HIDEYUKI , MISHUKU TOSHIO , ITOH ATSUO
IPC分类号： H01L31/0224 , H01L31/18 , H01L31/04 , H01L31/02 , H01L29/40
摘要： An amorphous semiconductor solar cell which comprises a glass substrate and a transparent electrode coated on the substrate. The device also comprises an amorphous semiconductor layer on the transparent electrode, and a rear electrode on the amorphous layer, wherein the average grain diameter of the surface of the transparent electrode ranges from 0.1 mu m to 2.5 mu m.

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