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    • 4. 发明申请
    • TEST STRUCTURES AND METHODS FOR MONITORING OR CONTROLLING A SEMICONDUCTOR FABRICATION PROCESS
    • 用于监测或控制半导体制造工艺的测试结构和方法
    • WO2006012388A3
    • 2006-12-14
    • PCT/US2005025821
    • 2005-07-22
    • KLA TENCOR TECH CORPMONAHAN KEVINEICHELBERGER BRADLEVY ADY
    • MONAHAN KEVINEICHELBERGER BRADLEVY ADY
    • G03F7/20
    • G03F7/70633G03F7/70625G03F7/70641G03F7/70683H01L22/34H01L2924/0002H01L2924/00
    • Various test structures and methods for monitoring or controlling a semiconductor fabrication process are provided. One test structure formed on a wafer as a monitor for a lithography process includes a bright field target (30) that includes first grating structures (32) . The test structure also includes a dark field target (34) that includes second grating structures (36) . The first and second grating structures have one or more characteristics that are substantially the same as one or more characteristics of device structures formed on the wafer. In addition, the test structure includes a phase shift target (38) having characteristics that are substantially the same as the characteristics of the bright field or dark field target except that grating structures (40) of the phase shift target are shifted in optical phase from the first or second grating structures. One or more characteristics of the targets can be measured and used to determine parameter (s) of the lithography process .
    • 提供了用于监测或控制半导体制造工艺的各种测试结构和方法。 在作为光刻处理的监视器的晶片上形成的一个测试结构包括包括第一光栅结构(32)的明场目标(30)。 测试结构还包括包括第二光栅结构(36)的暗场靶(34)。 第一和第二光栅结构具有与形成在晶片上的器件结构的一个或多个特性基本上相同的一个或多个特性。 此外,测试结构包括具有与亮场或暗场目标的特性基本相同的特性的相移目标(38),除了相移目标物的光栅结构(40)在光学相位 第一或第二光栅结构。 可以测量目标的一个或多个特征并用于确定光刻工艺的参数。
    • 8. 发明申请
    • SYSTEMS AND METHODS FOR MITIGATING VARIANCES ON A PATTERNED WAFER USING A PREDICTION MODEL
    • 使用预测模型减少图形波形上的变量的系统和方法
    • WO2006113145A2
    • 2006-10-26
    • PCT/US2006012846
    • 2006-04-07
    • KLA TENCOR TECH CORPWATSON STERLING GLEVY ADYMACK CHRIS ASTOKOWSKI STANLEY ESAIDIN ZAIN K
    • WATSON STERLING GLEVY ADYMACK CHRIS ASTOKOWSKI STANLEY ESAIDIN ZAIN K
    • G06F17/50G03F1/00
    • G03F1/84G03F1/36Y10S430/146
    • Disclosed are systems and methods for mitigating variances (e.g., critical dimension variances) on a patterned wafer are provided. In general, variances of a patterned wafer are predicted using one or more reticle fabrication and/or wafer processing models. The predicted variances are used to modify selected transparent portions of the reticle that is to be used to produce the patterned wafer. In a specific implementation, an optical beam, such as a femto-second laser, is applied to the reticle at a plurality of embedded positions, and the optical beam is configured to form specific volumes of altered optical properties within the transparent material of the reticle at the specified positions. These reticle volumes that are created at specific positions of the reticle result in varying amounts of light transmission or dose through the reticle at such specific positions so as to mitigate the identified variances on a wafer that is patterned using the modified reticle.
    • 公开了用于减轻图案化晶片上的方差(例如,临界尺寸方差)的系统和方法。 通常,使用一个或多个掩模版制造和/或晶片处理模型预测图案化晶片的变化。 预测的方差用于修改用于产生图案化晶片的掩模版的所选透明部分。 在具体实现中,诸如毫微微秒激光器的光束在多个嵌入位置被施加到掩模版,并且光束被配置为在掩模版的透明材料内形成改变的光学特性的特定体积 在指定位置。 在掩模版的特定位置处产生的这些掩模版体积在这样的特定位置处导致通过掩模版的光透射或剂量的变化量,以便减轻使用修改的掩模版图案化的晶片上识别的方差。