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1. 发明专利

JPH05233016A 失效
公开(公告)号：JPH05233016A
公开(公告)日：1993-09-10
申请号：JP3232192
申请日：1992-02-19
申请人： KEYENCE CO LTD
发明人： FUKUDA MASAHIKO
IPC分类号： G05B19/05
摘要： PURPOSE:To measure the intervals of pulse signals with a simple step without using any complicated instructions by reading an interval instruction with a program reading means and calculating the intervals of pulse signals with an interval calculating means. CONSTITUTION:At the time of activation, initial setting is executed by loading a system program stored in a ROM 20. When a programming console 30 is connected, program mode signals are transmitted from the console 30, and a sequence program is prepared and stored in an EEPROM 21. When run mode signals are transmitted from the console 30, a RUN mode processing is executed. In the RUN mode, one step of the sequence program is read and when the content shows an LDA instruction, the content designated by an operand is transferred to the internal register area 42 of an SRAM 19. When the read instruction shows an STA instruction, the operand stored in the internal register area 42 is transferred to the designated destination.

2. 发明专利

JPH0519913A INFORMATION READER/WRITER FOR ID SYSTEM 失效
公开(公告)号：JPH0519913A
公开(公告)日：1993-01-29
申请号：JP3558591
申请日：1991-02-04
申请人： KEYENCE CO LTD
发明人： FUKUDA MASAHIKO , KUKI TAIJI , UEKI KENGO , KARAKI TAKAYUKI
IPC分类号： B23Q41/00 , B65G47/49 , G01C9/00 , G01C9/12 , G05B19/418 , G06F1/32 , G06F15/02
摘要： PURPOSE:To reduce the burden of a power supply part at a data reader/writer to read/write information to a data carrier while being on-line connected to a head constituting an ID system. CONSTITUTION:An information reader/writer 7 is equipped with a key input circuit 74 for inputting information to be transmitted through a head 2 to the data carrier, liquid crystal display module 75 to display the information of communication with the head 2, and power source 7a to a back light 75a of the liquid crystal display module 75 and while communication between the head 2 and the data carrier, the supply of power to the back light 75a is cut off.

3. 发明专利

JPH0448004B2 失效
公开(公告)号：JPH0448004B2
公开(公告)日：1992-08-05
申请号：JP13954285
申请日：1985-06-26
申请人： KEYENCE CO LTD
发明人： FUKUDA MASAHIKO
IPC分类号： H03K17/78 , H03K17/08 , H03K17/94

4. 发明专利

JPS62189815A PHOTOELECTRIC SWITCH 失效
公开(公告)号：JPS62189815A
公开(公告)日：1987-08-19
申请号：JP3213886
申请日：1986-02-17
申请人： KEYENCE CO LTD
发明人： FUKUDA MASAHIKO
IPC分类号： H03K17/78
摘要： PURPOSE:To prevent malfunction due to interference light by detecting the case that a light signal generated from itself and a light signal generated from other photoelectric switch come simultaneously and neglecting the both. CONSTITUTION:A pulse modulation light from a projecting means 1 is received by a photodetection means 2 and detected by a detection circuit 3. Then a detection signal (d) from the detection circuit 3 is read serially sequentially by a shift register 5 in response to a clock pulse of a pulse oscillation circuit 7 to form parallel output signals e-g. Then a bit pattern detection circuit 11 discriminates it that a signal incoming in a specific bit pattern by a parallel output signal (g) made incident at the standard period is a signal being an interference light due to different periods. Then a strobe signal extraction circuit 19 generates a signal being the extraction of the detection signal and the interference light based on clear signals il, i2 being the frequency division of the clock pulse and signals (j, k).

5. 发明专利

JP2547106B2 失效
公开(公告)号：JP2547106B2
公开(公告)日：1996-10-23
申请号：JP1000890
申请日：1990-01-18
申请人： KEYENCE CO LTD
发明人： FUKUDA MASAHIKO , KUKI TAIJI , OKAMOTO YASUHIRO , NAKADE KAZUHIKO , UEKI KENGO
IPC分类号： G05B19/05

6. 发明专利

JPH064731A OPERATING STATE MONITOR DEVICE 失效
公开(公告)号：JPH064731A
公开(公告)日：1994-01-14
申请号：JP16586192
申请日：1992-06-24
申请人： KEYENCE CO LTD
发明人： FUKUDA MASAHIKO , KAKUBUCHI KOUICHI , TANAI NAOKI
IPC分类号： G07C3/00 , G06T1/00 , G08B23/00 , G08B25/00 , G06F15/62
摘要： PURPOSE:To record states before and after the change of the operating state with a low cost. CONSTITUTION:An operating state monitor device records picture data of an equipment picked up by a video camera on a VTR 4 to monitor the operating state of the monitor object. This device is provided with a compressing circuit 11, a FIFO memory circuit 12, an expanding circuit 13, and a control circuit 5. The compressing circuit 11 compresses picture data obtained by the video camera. The FIFO memory circuit 12 delays picture data compressed by the compressing circuit 11. The expanding circuit 12 expands the delay result of the FIFO memory circuit 12. The control circuit 5 records the expansion result of the expanding circuit 13 on the VTR 4 when the operating state is changed.

7. 发明专利

JPH0511683B2 失效
公开(公告)号：JPH0511683B2
公开(公告)日：1993-02-16
申请号：JP3213886
申请日：1986-02-17
申请人： KEYENCE CO LTD
发明人： FUKUDA MASAHIKO
IPC分类号： H03K17/78

8. 发明专利

JPH03214205A SEQUENCE CONTROLLER 失效
公开(公告)号：JPH03214205A
公开(公告)日：1991-09-19
申请号：JP1000890
申请日：1990-01-18
申请人： KEYENCE CO LTD
发明人： FUKUDA MASAHIKO , KUKI TAIJI , OKAMOTO YASUHIRO , NAKADE KAZUHIKO , UEKI KENGO
IPC分类号： G05B19/05
摘要： PURPOSE:To obtain an accurate clock pulse by providing a dividing circuit which divides the output of a clock oscillation circuit based on a dividing rate which is operated by a central processing means in response to a clock output instruction. CONSTITUTION:The system clocks are applied to a CPU 8 as well as to a counter 35. Then the counter 35 counts these system clocks and gives the count value to a comparator 25, and this comparator 25 compares the count-up value given from the CPU 8 with the count value of the counter 35 and then outputs the comparison match output 125 when the coincidence is obtained between both values. The output 125 is given to a reset input CLR or the counter 35 and therefore outputted for each count-up value of the system clocks. In addition, the output 125 is given to a control logic 55 and this logic 55 changes continuously the output to L from H and vice verse for each application of the output 125. Thus an accurate clock pulse is obtained.

9. 发明专利

JPS63196119A 2-STAGE PRESET COUNTER 失效
公开(公告)号：JPS63196119A
公开(公告)日：1988-08-15
申请号：JP2855887
申请日：1987-02-10
申请人： KEYENCE CO LTD
发明人： FUKUDA MASAHIKO , SAKAEDA REI
IPC分类号： H03K21/00 , H03K23/66
摘要： PURPOSE:To eliminate troubles in the assembling and maintenance by counting a clock pulse to be counted, comparing a count at the discriminating timing from a timing pulse with two preset values to discriminate the quantity of value thereby eliminating the need for a decoder circuit and a timing circuit at the output side. CONSTITUTION:Receiving a clock pulse ck to be counted after the count is made 0, a microcomputer 1 discriminates that a timing pulse Pt does not yet reaches an H level, counts the pulse ck, discriminates whether or not the count is an intermediate value between two preset values SET1, SET2 when the pulse Pt rises and generates no output in case of the intermediate value. On the other hand, if the count of the pulse ck exceeds the high preset value although the pulse Pt does not rise yet, an output is given at an output terminal OUT. Even when the count does not reach the lower preset although the pulse Pt does not rise yet, an output is given from the output terminal OUT. Then in any case, the output is cleared while awaiting the trailing of the pulse Pt to make the count zero.

10. 发明专利

JPS6349802A PROGRAMMABLE CONTROLLER 失效
公开(公告)号：JPS6349802A
公开(公告)日：1988-03-02
申请号：JP19376286
申请日：1986-08-19
申请人： KEYENCE CO LTD
发明人： TODA JITSUO , FUKUDA MASAHIKO , TABUCHI ICHIRO , YAMAZAKI YOSHINORI
IPC分类号： G05B19/05 , G05B19/02
摘要： PURPOSE:To obtain a programmable controller having a high response speed to the change of an input signal by catching the rise or fall of the signal change by a flip-flop FF. CONSTITUTION:The input signal of an input signal processing part 17 is set to the desired polarity by a polarity switching circuit 12. When an output signal showing an abnormal state is supplied to an FF14, the FF14 transmits this output signal to an interruption control circuit 16. A CPU 1 receives an interruption signal and discontinues temporarily the normal arithmetic processing action to specify the signal change of a controlled system that caused an interruption. Then the CPU 1 processes the abnormal state based on an interruption signal processing program set previously. An action inhibiting signal is outputted to the corresponding FF14 from an FF control circuit 15 with a controlled system that is not required to give a prompt response to the signal change. Thus the FF14 never works even with input of the output signal of an input circuit that is due to the signal change of the controlled system.

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