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1. 发明申请

US20170053825A1 SEMICONDUCTOR DEVICES HAVING FIN FIELD EFFECT TRANSISTORS WITH A SINGLE LINER PATTERN IN A FIRST REGION AND A DUAL LINER PATTERN IN A SECOND REGION AND METHODS FOR MANUFACTURING THE SAME 审中-公开
标题翻译：具有第一区域中的单个衬板图案的第二区域中的具有场效应晶体管的半导体器件和用于制造其的方法
公开(公告)号：US20170053825A1
公开(公告)日：2017-02-23
申请号：US14831087
申请日：2015-08-20
申请人： KANG-ILL SEO , BOMSOO KIM , JI-HOON CHA
发明人： KANG-ILL SEO , BOMSOO KIM , JI-HOON CHA
IPC分类号： H01L21/762 , H01L21/311
CPC分类号： H01L21/76224 , H01L21/31144 , H01L21/823821 , H01L21/823878 , H01L27/0924
摘要： A method for manufacturing a semiconductor device includes forming a first active pattern in a first region of a substrate and a second active pattern in a second region of the substrate, wherein the first and second active patterns project from the substrate, forming a second liner pattern on the substrate and the second active pattern in the second region, wherein the second liner pattern has a second polarity, forming a first liner pattern on the substrate and the first active pattern in the first region, wherein the first liner pattern has a first polarity different from the second polarity, forming an isolation pattern on the first liner pattern in the first region and the second liner pattern in the second region, and exposing the first active pattern and the second active pattern by recessing the isolation pattern.
摘要翻译：一种制造半导体器件的方法包括在衬底的第一区域中形成第一有源图案和在衬底的第二区域中形成第二有源图案，其中第一和第二有源图案从衬底突出，形成第二衬垫图案在所述基板上和所述第二区域中的所述第二有源图案，其中所述第二衬垫图案具有第二极性，在所述基板上形成第一衬垫图案和所述第一区域中的所述第一有源图案，其中所述第一衬垫图案具有第一极性与第二极性不同，在第一区域中的第一衬垫图案和第二区域中的第二衬垫图案上形成隔离图案，并且通过凹陷隔离图案来暴露第一活动图案和第二活动图案。

2. 发明申请

US20160204262A1 INTEGRATED CIRCUIT DEVICES HAVING AIR-GAP SPACERS AND METHODS OF MANUFACTURING THE SAME 审中-公开
公开(公告)号：US20160204262A1
公开(公告)日：2016-07-14
申请号：US15079623
申请日：2016-03-24
申请人： KANG-ILL SEO , JIN-WOOK LEE
发明人： KANG-ILL SEO , JIN-WOOK LEE
IPC分类号： H01L29/78 , H01L29/51 , H01L29/49
CPC分类号： H01L29/7851 , H01L21/823468 , H01L23/485 , H01L27/088 , H01L29/4983 , H01L29/518 , H01L2924/0002 , H01L2924/00
摘要： Integrated circuit devices having a cavity and methods of manufacturing the integrated circuit devices are provided. The integrated circuit devices may include a pair of spacers, which define a recess. The integrated circuit device may also include a lower conductive pattern in the recess and an upper conductive pattern on the lower conductive pattern. The upper conductive pattern may have an etch selectivity with respect to the lower conductive pattern and may expose an upper surface of the lower conductive pattern adjacent a sidewall of the upper conductive pattern. An inner sidewall of one of the pair of spacers, the upper surface of the lower conductive pattern and the sidewall of the upper conductive pattern may define a space and a capping pattern may be formed on the upper conductive pattern to seal a top portion of the space, such that a cavity is disposed under the capping pattern.

3. 发明申请

US20160013309A1 SEMICONDUCTOR DEVICE HAVING GATE-ALL-AROUND TRANSISTOR AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：具有门极绕晶体管的半导体器件及其制造方法
公开(公告)号：US20160013309A1
公开(公告)日：2016-01-14
申请号：US14330305
申请日：2014-07-14
申请人： DONG-IL BAE , KANG-ILL SEO
发明人： DONG-IL BAE , KANG-ILL SEO
IPC分类号： H01L29/78 , H01L29/66 , H01L27/11 , H01L27/088 , H01L27/092
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L27/0886 , H01L27/092 , H01L27/0924 , H01L27/1104 , H01L27/1116 , H01L29/42392 , H01L29/66545 , H01L29/66795 , H01L29/785 , H01L29/78618 , H01L29/78654 , H01L29/78684 , H01L29/78696 , H01L2029/7858
摘要： A semiconductor device includes a fin structure disposed on a substrate, a sacrificial layer pattern disposed on the fin structure, an active layer pattern disposed on the sacrificial layer pattern, and a gate dielectric layer and a gate electrode layer extending through the sacrificial layer pattern and surrounding a portion of the active layer pattern.
摘要翻译：半导体器件包括设置在衬底上的翅片结构，设置在鳍结构上的牺牲层图案，设置在牺牲层图案上的有源层图案，以及延伸穿过牺牲层图案的栅极电介质层和栅电极层，以及围绕有源层图案的一部分。

4. 发明申请

US20150214220A1 INTEGRATED CIRCUIT DEVICES HAVING AIR-GAP SPACERS AND METHODS OF MANUFACTURING THE SAME 有权
标题翻译：具有空气隙空间的集成电路装置及其制造方法
公开(公告)号：US20150214220A1
公开(公告)日：2015-07-30
申请号：US14165721
申请日：2014-01-28
申请人： KANG-ILL SEO , JIN-WOOK LEE
发明人： KANG-ILL SEO , JIN-WOOK LEE
IPC分类号： H01L27/088 , H01L23/532 , H01L23/528
CPC分类号： H01L29/7851 , H01L21/823468 , H01L23/485 , H01L27/088 , H01L29/4983 , H01L29/518 , H01L2924/0002 , H01L2924/00
摘要： Integrated circuit devices having a cavity and methods of manufacturing the integrated circuit devices are provided. The integrated circuit devices may include a pair of spacers, which define a recess. The integrated circuit device may also include a lower conductive pattern in the recess and an upper conductive pattern on the lower conductive pattern. The upper conductive pattern may have an etch selectivity with respect to the lower conductive pattern and may expose an upper surface of the lower conductive pattern adjacent a sidewall of the upper conductive pattern. An inner sidewall of one of the pair of spacers, the upper surface of the lower conductive pattern and the sidewall of the upper conductive pattern may define a space and a capping pattern may be formed on the upper conductive pattern to seal a top portion of the space, such that a cavity is disposed under the capping pattern.
摘要翻译：提供具有空腔的集成电路器件和制造集成电路器件的方法。集成电路器件可以包括限定凹部的一对间隔件。集成电路器件还可以包括凹陷中的下导电图案和下导电图案上的上导电图案。上导电图案可以具有相对于下导电图案的蚀刻选择性，并且可以暴露邻近上导电图案的侧壁的下导电图案的上表面。一对间隔物中的一个的内侧壁，下导电图案的上表面和上导电图案的侧壁可以限定空间，并且可以在上导电图案上形成封盖图案，以密封上导电图案的顶部空间，使得空腔设置在封盖图案下方。

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