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1. 发明申请

US20150249559A1 Clock-Embedded Vector Signaling Codes 有权
标题翻译：时钟嵌入矢量信令码
公开(公告)号：US20150249559A1
公开(公告)日：2015-09-03
申请号：US14636098
申请日：2015-03-02
申请人： Kandou Labs SA
发明人： Amin Shokrollahi , Brian Holden , Richard Simpson
IPC分类号： H04L25/08 , H04L25/03
CPC分类号： H04L25/49 , H04L25/03006 , H04L25/03057 , H04L25/08 , H04L25/085
摘要： Vector signaling codes providing guaranteed numbers of transitions per unit transmission interval are described, along with methods and systems for their generation and use. The described architecture may include multiple communications sub-systems, each having its own communications wire group or sub-channel, clock-embedded signaling code, pre- and post-processing stages to guarantee the desired code transition density, and global encoding and decoding stages to first distribute data elements among the sub-systems, and then to reconstitute the received data from its received sub-system elements.
摘要翻译：描述了提供每单位传输间隔保证数量的转换的向量信令码，以及用于其生成和使用的方法和系统。所描述的架构可以包括多个通信子系统，每个子系统具有其自己的通信线组或子信道，时钟嵌入式信令代码，预处理和后处理阶段以保证期望的代码转换密度，以及全局编码和解码阶段首先在子系统之间分配数据元素，然后从接收到的子系统元素重建接收到的数据。

2. 发明授权

US09071476B2 Methods and systems for high bandwidth chip-to-chip communications interface 有权
公开(公告)号：US09071476B2
公开(公告)日：2015-06-30
申请号：US14199960
申请日：2014-03-06
申请人： Kandou Labs, SA
发明人： John Fox , Brian Holden , Ali Hormati , Peter Hunt , John D. Keay , Amin Shokrollahi , Richard Simpson , Anant Singh , Andrew Kevin John Stewart , Giuseppe Surace , Roger Ulrich
IPC分类号： H03K9/00 , H04L25/02
CPC分类号： H04L25/028 , H04L25/0292
摘要： Systems and methods are described for transmitting data over physical channels to provide a high bandwidth, low latency interface between integrated circuit chips with low power utilization. Communication is performed using group signaling over multiple wires using a vector signaling code, where each wire carries a low-swing signal that may take on more than two signal values.

3. 发明申请

US20140254642A1 Methods and Systems for High Bandwidth Chip-to-Chip Communications Interface 有权
标题翻译：高带宽芯片到芯片通信接口的方法和系统
公开(公告)号：US20140254642A1
公开(公告)日：2014-09-11
申请号：US14199960
申请日：2014-03-06
申请人： Kandou Labs, SA
发明人： John Fox , Brian Holden , Ali Hormati , Peter Hunt , John D. Keay , Amin Shokrollahi , Richard Simpson , Anant Singh , Andrew Kevin John Stewart , Giuseppe Surace , Roger Ulrich
IPC分类号： H04L25/02
CPC分类号： H04L25/028 , H04L25/0292
摘要： Systems and methods are described for transmitting data over physical channels to provide a high bandwidth, low latency interface between integrated circuit chips with low power utilization. Communication is performed using group signaling over multiple wires using a vector signaling code, where each wire carries a low-swing signal that may take on more than two signal values.
摘要翻译：描述了用于通过物理信道传输数据的系统和方法，以在具有低功率利用率的集成电路芯片之间提供高带宽，低延迟的接口。使用矢量信令码通过多条线路使用组信令进行通信，其中每条线路携带可能承受多于两个信号值的低摆动信号。

4. 发明授权

US09300503B1 Methods and systems for skew tolerance in and advanced detectors for vector signaling codes for chip-to-chip communication 有权
标题翻译：用于芯片到芯片通信的矢量信令码的偏差容限和高级检测器的方法和系统
公开(公告)号：US09300503B1
公开(公告)日：2016-03-29
申请号：US13842740
申请日：2013-03-15
申请人： Kandou Labs, SA
发明人： Brian Holden , Amin Shokrollahi , Anant Singh
IPC分类号： H03K9/00 , H04L27/06 , H04L25/08
CPC分类号： H04B17/364 , G06F13/00 , H04B3/00 , H04B3/02 , H04B5/0031 , H04B5/0081 , H04L1/0041 , H04L1/0643 , H04L7/043 , H04L7/048 , H04L25/0268 , H04L25/0272 , H04L25/028 , H04L25/0292 , H04L25/03019 , H04L25/08 , H04L25/4925 , H04L2001/0096 , Y02D70/26 , Y02D70/42
摘要： Advanced detectors for vector signaling codes are disclosed which utilize multi-input comparators, generalized on-level slicing, reference generation based on maximum swing, and reference generation based on recent values. Vector signaling codes communicate information as groups of symbols which, when transmitted over multiple communications channels, may be received as mixed sets of symbols from different transmission groups due to propagation time variations between channels. Systems and methods are disclosed which compensate receivers and transmitters for these effects and/or utilize codes having increased immunity to such variations, and circuits are described that efficiently implement their component functions.
摘要翻译：公开了用于矢量信令代码的高级检测器，其利用多输入比较器，广义的电平切片，基于最大摆幅的参考生成以及基于最近值的参考生成。矢量信令代码将信息作为一组符号进行通信，这些符号组在由多个通信信道发送时可能由于信道之间的传播时间变化而被从不同的传输组接收为混合的符号集合。公开了对这些效应的接收机和发射机进行补偿和/或利用对这种变化具有增强的抗扰性的代码的系统和方法，并且描述了有效地实现其组件功能的电路。

5. 发明公开

US20240106686A1 PRE-SCALER FOR ORTHOGONAL DIFFERENTIAL VECTOR SIGNALLING 审中-公开
公开(公告)号：US20240106686A1
公开(公告)日：2024-03-28
申请号：US18519830
申请日：2023-11-27
申请人： KANDOU LABS SA
发明人： Brian Holden
IPC分类号： H04L25/02 , H04L27/26
CPC分类号： H04L25/0272 , H04L27/2626
摘要： Orthogonal differential vector signalling (ODVS) techniques are described. The ODVS encoding schemes described herein generate one sub-channel for each bit by multiplying each bit by a different row in a transmitter encoding matrix to produce a set of sub-channels. Each wire carries a signal that is a superposition of elements from all of the sub-channels in the set. The transmitter encoding matrix is selected such that its rows (i.e. sub-channels) are mutual orthogonal. This means that the receiver can decode the signals received from all wires in concert to reliably recover the original bits. The transmitter encoding matrix applies weights to each sub-channel of the set, with the absolute magnitude of the weights decreasing as the number of wires associated with the respective sub-channel increases.

6. 发明授权

US09363114B2 Clock-embedded vector signaling codes 有权
标题翻译：时钟嵌入矢量信令码
公开(公告)号：US09363114B2
公开(公告)日：2016-06-07
申请号：US14636098
申请日：2015-03-02
申请人： Kandou Labs SA
发明人： Amin Shokrollahi , Brian Holden , Richard Simpson
IPC分类号： H04L25/00 , H04L25/08 , H04L25/03 , H04L25/49
CPC分类号： H04L25/49 , H04L25/03006 , H04L25/03057 , H04L25/08 , H04L25/085
摘要： Vector signaling codes providing guaranteed numbers of transitions per unit transmission interval are described, along with methods and systems for their generation and use. The described architecture may include multiple communications sub-systems, each having its own communications wire group or sub-channel, clock-embedded signaling code, pre- and post-processing stages to guarantee the desired code transition density, and global encoding and decoding stages to first distribute data elements among the sub-systems, and then to reconstitute the received data from its received sub-system elements.
摘要翻译：描述了提供每单位传输间隔保证数量的转换的向量信令码，以及用于其生成和使用的方法和系统。所描述的架构可以包括多个通信子系统，每个子系统具有其自己的通信线组或子信道，时钟嵌入式信令代码，预处理和后处理阶段以保证期望的代码转换密度，以及全局编码和解码阶段首先在子系统之间分配数据元素，然后从接收到的子系统元素重建接收到的数据。

7. 发明授权

US09251873B1 Methods and systems for pin-efficient memory controller interface using vector signaling codes for chip-to-chip communications 有权
标题翻译：使用矢量信令代码进行芯片到芯片通信的针对高效存储器控制器接口的方法和系统
公开(公告)号：US09251873B1
公开(公告)日：2016-02-02
申请号：US14108316
申请日：2013-12-16
申请人： Kandou Labs SA
发明人： John Fox , Brian Holden , Amin Shokrollahi , Anant Singh , Giuseppe Surace
IPC分类号： G11C7/10 , G11C7/22 , G06F13/42 , G06F13/16
CPC分类号： G11C7/22 , G06F13/1689 , G06F13/385 , G06F13/4243 , G11C7/10 , G11C7/1072 , G11C8/10
摘要： Systems and methods are described for transmitting data over physical channels to provide a high speed, low latency interface such as between a memory controller and memory devices. Controller-side and memory-side embodiments of such channel interfaces are disclosed which require a low pin count and have low power utilization. In some embodiments of the invention, different voltage, current, etc. levels are used for signaling and more than two levels may be used, such as a vector signaling code wherein each wire signal may take on one of four signal values.
摘要翻译：描述了通过物理信道传输数据以提供诸如存储器控制器和存储器件之间的高速，低延迟接口的系统和方法。公开了这样的信道接口的控制器侧和存储器侧实施例，其需要低引脚数并具有低功率利用率。在本发明的一些实施例中，不同的电压，电流等级用于信令，并且可以使用多于两个级别，例如矢量信令代码，其中每个有线信号可以采用四个信号值之一。

8. 发明授权

US09106238B1 Sorting decoder 有权
标题翻译：排序解码器
公开(公告)号：US09106238B1
公开(公告)日：2015-08-11
申请号：US13844331
申请日：2013-03-15
申请人： Kandou Labs, SA
发明人： Harm Cronie , Brian Holden
IPC分类号： H03M1/36 , H03M7/00 , H03M1/18
CPC分类号： H03M7/00 , G06F11/1072 , G06F12/0207 , H03M1/18 , Y02D10/13
摘要： A sorting decoder captures the rank-order of a set of input analog signals in the digital domain using simple logic components such as self-timed first state elements, without requiring conventional analog-to-digital signal converters. The analog signals are each compared against a monotonic dynamic reference and the resulting comparisons are snapshot by a self-timed first state element for each input signal, or the last member of a sorted collection of input signals, at the time when it reaches the reference signal, so that a different snapshot representing the signal value ranking relative to the other signal values is produced for each input signal. The resulting rank-order estimation snapshots are binary signals that can then be further processed by a simple sorting logic circuit based on elementary logic components.
摘要翻译：排序解码器使用诸如自定时第一状态元素之类的简单逻辑组件来捕获数字域中的一组输入模拟信号的秩次，而不需要常规的模数转换器。模拟信号各自与单调动态参考进行比较，并且所得到的比较是对于每个输入信号的自定时第一状态元素或输入信号的排序集合的最后一个成员在到达参考时的快照信号，使得针对每个输入信号产生表示相对于其它信号值排列的信号值的不同快照。所得到的秩序估计快照是二进制信号，然后可以通过基于基本逻辑分量的简单分类逻辑电路进一步处理二进制信号。

9. 发明授权

US11831472B1 Pre-scaler for orthogonal differential vector signalling 有权
公开(公告)号：US11831472B1
公开(公告)日：2023-11-28
申请号：US17931448
申请日：2022-09-12
申请人： KANDOU LABS SA
发明人： Brian Holden
IPC分类号： H04L25/02 , H04L27/26
CPC分类号： H04L25/0272 , H04L27/2626
摘要： Pre-scaled orthogonal differential vector signalling (ODVS) techniques are described. The ODVS encoding schemes described herein generate one sub-channel for each bit by multiplying each bit by a different row in a transmitter encoding matrix to produce a set of sub-channels. Each wire carries a signal that is a superposition of elements from all of the sub-channels in the set. The transmitter encoding matrix is selected such that its rows (i.e. sub-channels) are mutual orthogonal. This means that the receiver can decode the signals received from all wires in concert to reliably recover the original bits. The transmitter encoding matrix is a Hadamard matrix in some cases. This disclosure is particularly focussed on ODVS techniques that apply a scaling factor, termed a ‘pre-scaler’, to a weaker sub-channel or sub-channels within the set of sub-channels so as to boost that/those sub-channel(s) relative to the other sub-channels.

10. 发明授权

US09461862B2 Orthogonal differential vector signaling codes with embedded clock 有权
标题翻译：具有嵌入式时钟的正交差分矢量信令码
公开(公告)号：US09461862B2
公开(公告)日：2016-10-04
申请号：US14816896
申请日：2015-08-03
申请人： Kandou Labs SA
发明人： Brian Holden , Amin Shokrollahi
IPC分类号： H04L27/04 , H04L27/26
CPC分类号： H04L27/2637 , G06F13/426 , G11C7/1006 , G11C7/1066 , G11C7/1093 , G11C7/222 , G11C11/4076 , G11C11/4093 , H04L25/4919 , Y02D10/14 , Y02D10/151
摘要： Orthogonal differential vector signaling codes are described which support encoded sub-channels allowing transport of distinct but temporally aligned data and clocking signals over the same transport medium. Embodiments providing enhanced LPDDR interfaces are described which are suitable for implementation in both conventional high-speed CMOS and DRAM integrated circuit processes.
摘要翻译：描述了正交差分矢量信令码，其支持编码的子信道，允许在相同的传输介质上传输不同但时间上对准的数据和时钟信号。描述了提供增强的LPDDR接口的实施例，其适用于在传统的高速CMOS和DRAM集成电路过程中实现。

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