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1. 发明申请

WO2013080594A1 DEVICE AND AUTHENTICATION METHOD THEREFOR 审中-公开
标题翻译：其设备和认证方法
公开(公告)号：WO2013080594A1
公开(公告)日：2013-06-06
申请号：PCT/JP2012/065934
申请日：2012-06-15
申请人： KABUSHIKI KAISHA TOSHIBA , NAGAI, Yuji , KATO, Taku , MATSUSHITA, Tatsuyuki , SUZUKI, Toshihiro , SHIBATA, Noboru
发明人： NAGAI, Yuji , KATO, Taku , MATSUSHITA, Tatsuyuki , SUZUKI, Toshihiro , SHIBATA, Noboru
IPC分类号： H04L9/08 , H04L9/32 , G11B20/00
CPC分类号： H04L9/0816 , G11B20/00362 , G11B20/00427 , H04L9/0822 , H04L9/0833 , H04L9/0897 , H04L9/32 , H04L2209/601
摘要： According to one embodiment, an authentication method includes generating, by the memory, first authentication information by calculating secret identification information with a memory session key in one-way function operation, transmitting encrypted secret identification information, a family key block, and the first authentication information to a host, and generating, by the host, second authentication information by calculating the secret identification information generated by decrypting the encrypted secret identification information with the host session key in one-way function operation. The method further includes comparing, by the host, the first authentication information with the second authentication information.
摘要翻译：根据一个实施例，一种认证方法包括：通过在单向功能操作中用存储器会话密钥计算秘密识别信息，通过存储器生成第一认证信息，发送加密的秘密识别信息，家庭密钥块和第一认证信息发送到主机，并且由主机通过计算通过用单向功能操作中的主机会话密钥对加密的秘密识别信息进行解密而生成的秘密识别信息来生成第二认证信息。该方法还包括由主机将第一认证信息与第二认证信息进行比较。

2. 发明申请

WO2013080595A1 SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：半导体存储器件
公开(公告)号：WO2013080595A1
公开(公告)日：2013-06-06
申请号：PCT/JP2012/065935
申请日：2012-06-15
申请人： KABUSHIKI KAISHA TOSHIBA , NAGAI, Yuji , SUZUKI, Toshihiro , SHIBATA, Noboru , KATO, Taku , MATSUSHITA, Tatsuyuki
发明人： NAGAI, Yuji , SUZUKI, Toshihiro , SHIBATA, Noboru , KATO, Taku , MATSUSHITA, Tatsuyuki
IPC分类号： H04L9/08 , H04L9/32 , G11B20/00
CPC分类号： H04L9/0816 , G11B20/00086 , G11B20/00115 , G11B20/0021 , G11B2220/2516 , G11B2220/60 , H04L9/0822 , H04L9/0833 , H04L9/0897 , H04L9/32 , H04L2209/601
摘要： According to one embodiment, a device includes a first memory area to store a first key. A second memory area stores encrypted secret identification (ID) information generated from secret ID information with a family key. A third memory area stores a family key block including data generated from the family key with an ID key. An authentication module performs authentication. A second key is generated from a first number with the first key, a session key is generated from a random number with the second key, and authentication information is generated from the secret ID information with the session key. The encrypted secret ID information, family key block and the authentication information is output.
摘要翻译：根据一个实施例，设备包括用于存储第一密钥的第一存储区域。第二存储区域存储从秘密ID信息生成的加密的秘密标识（ID）信息与家庭密钥。第三存储区域存储包括具有ID密钥的家庭密钥产生的数据的家庭密钥块。认证模块执行认证。从具有第一密钥的第一号码生成第二密钥，从具有第二密钥的随机数生成会话密钥，并且从具有会话密钥的秘密ID信息生成认证信息。输出加密的秘密ID信息，家庭密钥块和认证信息。

3. 发明申请

WO2013080593A1 SEMICONDUCTOR STORAGE DEVICE 审中-公开
标题翻译：半导体存储设备
公开(公告)号：WO2013080593A1
公开(公告)日：2013-06-06
申请号：PCT/JP2012/065933
申请日：2012-06-15
申请人： KABUSHIKI KAISHA TOSHIBA , NAGAI, Yuji , SUZUKI, Toshihiro , SHIBATA, Noboru , KATO, Taku , MATSUSHITA, Tatsuyuki
发明人： NAGAI, Yuji , SUZUKI, Toshihiro , SHIBATA, Noboru , KATO, Taku , MATSUSHITA, Tatsuyuki
IPC分类号： H04L9/08 , H04L9/32 , G11B20/00
CPC分类号： H04L9/0816 , G11B20/00086 , G11B20/00115 , G11B20/0021 , G11B2220/2516 , G11B2220/60 , H04L9/0822 , H04L9/0833 , H04L9/0897 , H04L9/32 , H04L2209/601
摘要： According to one embodiment, a device includes a storage and an authenticator. The storage includes a first area, a second area and a third area. The first area stores NKey and SecretID, the second area stores index information. E-SecretID is generated by SecretID. The third area stores FKB including information generated by FKey. The authenticator authenticates the external device. HKey is generated by an AES encryption calculating using NKey and HC. A SKey is generated by an AES encryption process using HKey and RN. A one-way conversion calculating is performed. E-SecretID, FKB and Oneway-ID are output to the external device. The index information is read from the second area.
摘要翻译：根据一个实施例，一种设备包括存储器和认证器。存储器包括第一区域，第二区域和第三区域。第一个区域存储NKey和SecretID，第二个区域存储索引信息。 E-SecretID由SecretID生成。第三个区域存储FKB，包括FKey生成的信息。验证器验证外部设备。 HKey由使用NKey和HC的AES加密计算产生。通过使用HKey和RN的AES加密过程生成SKey。执行单向转换计算。 E-SecretID，FKB和Oneway-ID被输出到外部设备。从第二区域读取索引信息。

4. 发明申请

WO2013080592A1 MEMORY 审中-公开
标题翻译：记忆
公开(公告)号：WO2013080592A1
公开(公告)日：2013-06-06
申请号：PCT/JP2012/065932
申请日：2012-06-15
申请人： KABUSHIKI KAISHA TOSHIBA , NAGAI, Yuji , SUZUKI, Toshihiro , SHIBATA, Noboru , KATO, Taku , MATSUSHITA, Tatsuyuki
发明人： NAGAI, Yuji , SUZUKI, Toshihiro , SHIBATA, Noboru , KATO, Taku , MATSUSHITA, Tatsuyuki
IPC分类号： H04L9/08 , H04L9/32 , G11B20/00
CPC分类号： H04L9/0816 , G11B20/00086 , G11B20/0021 , G11B20/00217 , G11B20/00253 , H04L9/0822 , H04L9/0833 , H04L9/0897 , H04L9/32 , H04L2209/601
摘要： According to one embodiment, a memory includes a first storage region capable of storing first key (NKey) information, and secret identification information (SecretID) unique to the authenticate, reading and writing data from and to the first storage region from an outside of the authenticatee being inhibited at least after the authenticatee is shipped.
摘要翻译：根据一个实施例，存储器包括能够存储第一密钥（NKey）信息的第一存储区域和从第一存储区域的外部识别，读取和写入数据的唯一的秘密识别信息（SecretID）至少在验证者发货后，验证者被禁止。

5. 发明申请

WO2009031675A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM 审中-公开
标题翻译：非易失性半导体存储器件和存储器系统
公开(公告)号：WO2009031675A1
公开(公告)日：2009-03-12
申请号：PCT/JP2008/066141
申请日：2008-09-02
申请人： KABUSHIKI KAISHA TOSHIBA , HONMA, Mitsuaki , SHIBATA, Noboru
发明人： HONMA, Mitsuaki , SHIBATA, Noboru
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06 , H01L27/10
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C2211/5646
摘要： A semiconductor memory device executes a writing operation based on a first bit assignment pattern at the time of writing. The first bit assignment pattern is created such that pieces of x-bit data assigned to adjacent threshold distributions have only a one-bit difference therebetween and an alignment of data on the same digit of 2x pieces of x-bit data corresponding to an alignment of 2x pieces of threshold distributions contains at least two transition points of "0" and "1". The semiconductor memory device operates at the time of reading such that a read voltage corresponding to the transition points of "0" and "1" is applied to the word line on a page basis to determine x-bit data stored in the memory cell one-bit by one-bit based on the first assignment pattern. The page contains a set of data on the same digit bit in pieces of x-bit data stored in the memory cells connected to the word line.
摘要翻译：半导体存储器件在写入时基于第一位分配模式执行写入操作。第一位分配模式被创建，使得分配给相邻阈值分布的X位数据片段之间只有一位差异，并且对应于与x位数据对齐的2个x位数据的相同数位上的数据对齐 2个阈值分布包含至少两个转换点“0”和“1”。半导体存储器件在读取时操作，使得对应于“0”和“1”的转换点的读取电压在页面上施加到字线，以确定存储在存储器单元中的x位数据 - 基于第一个分配模式位1比特。该页面包含存储在连接到字线的存储单元中的x位数据的相同位数位上的一组数据。

6. 发明申请

WO2005048266A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：WO2005048266A1
公开(公告)日：2005-05-26
申请号：PCT/JP2004/003785
申请日：2004-03-19
申请人： KABUSHIKI KAISHA TOSHIBA , SHIBATA, Noboru
发明人： SHIBATA, Noboru
IPC分类号： G11C11/56
CPC分类号： G11C11/5628 , G11C11/5621 , G11C16/0483 , G11C16/3454 , G11C2211/5621 , G11C2211/5642
摘要： A page mode multi-level NAND-type memory employs two different verify levels per data state and comprises a first data storage circuit which is connected to a memory cell and which stores externally inputted data of a first logic level or a second logic level, a second data storage circuit which is connected to the memory cell and which stores the data of the first logic level or second logic level read from the memory cell, and a control circuit which controls the memory cell and the first and second data storage circuits and which reproduces the externally inputted data and writing the data into the memory cell.
摘要翻译：页面模式多级NAND型存储器对每个数据状态采用两个不同的验证电平，并且包括连接到存储器单元并且存储外部输入的第一逻辑电平或第二逻辑电平的数据的第一数据存储电路，第二数据存储电路，连接到存储单元，并存储从存储单元读取的第一逻辑电平或第二逻辑电平的数据;以及控制电路，其控制存储单元以及第一和第二数据存储电路，再现外部输入的数据并将数据写入存储单元。

7. 发明公开

EP2786520A1 MEMORY 失效转让
标题翻译：斯派克
公开(公告)号：EP2786520A1
公开(公告)日：2014-10-08
申请号：EP12746397.4
申请日：2012-06-15
申请人： Kabushiki Kaisha Toshiba
发明人： NAGAI, Yuji , SUZUKI, Toshihiro , SHIBATA, Noboru , KATO, Taku , MATSUSHITA, Tatsuyuki
IPC分类号： H04L9/08 , H04L9/32 , G11B20/00
CPC分类号： H04L9/0816 , G11B20/00086 , G11B20/0021 , G11B20/00217 , G11B20/00253 , H04L9/0822 , H04L9/0833 , H04L9/0897 , H04L9/32 , H04L2209/601
摘要： According to one embodiment, a memory includes a first storage region capable of storing first key (NKey) information, and secret identification information (SecretID) unique to the authenticate, reading and writing data from and to the first storage region from an outside of the authenticatee being inhibited at least after the authenticatee is shipped.
摘要翻译：根据一个实施例，存储器包括能够存储第一密钥（NKey）信息的第一存储区域以及从第一存储区域的外部认证，读取和写入数据所特有的秘密识别信息（SecretID）至少在验证人发货后，验证者被禁止。

8. 发明公开

EP2786521A1 DEVICE AND AUTHENTICATION METHOD THEREFOR 有权转让
标题翻译：设备和认证及其方法
公开(公告)号：EP2786521A1
公开(公告)日：2014-10-08
申请号：EP12746398.2
申请日：2012-06-15
申请人： Kabushiki Kaisha Toshiba
发明人： NAGAI, Yuji , KATO, Taku , MATSUSHITA, Tatsuyuki , SUZUKI, Toshihiro , SHIBATA, Noboru
IPC分类号： H04L9/08 , H04L9/32 , G11B20/00
CPC分类号： H04L9/0816 , G11B20/00362 , G11B20/00427 , H04L9/0822 , H04L9/0833 , H04L9/0897 , H04L9/32 , H04L2209/601
摘要： According to one embodiment, an authentication method includes generating, by the memory, first authentication information by calculating secret identification information with a memory session key in one-way function operation, transmitting encrypted secret identification information, a family key block, and the first authentication information to a host, and generating, by the host, second authentication information by calculating the secret identification information generated by decrypting the encrypted secret identification information with the host session key in one-way function operation. The method further includes comparing, by the host, the first authentication information with the second authentication information.

9. 发明授权

EP2786523B1 SEMICONDUCTOR MEMORY DEVICE 有权转让
标题翻译：半导体存储器件
公开(公告)号：EP2786523B1
公开(公告)日：2015-09-23
申请号：EP12751376.0
申请日：2012-06-15
申请人： Kabushiki Kaisha Toshiba
发明人： NAGAI, Yuji , SUZUKI, Toshihiro , SHIBATA, Noboru , KATO, Taku , MATSUSHITA, Tatsuyuki
IPC分类号： H04L9/08 , H04L9/32 , G11B20/00
CPC分类号： H04L9/0816 , G11B20/00086 , G11B20/00115 , G11B20/0021 , G11B2220/2516 , G11B2220/60 , H04L9/0822 , H04L9/0833 , H04L9/0897 , H04L9/32 , H04L2209/601

10. 发明授权

EP2786520B1 MEMORY 失效转让
标题翻译：记忆
公开(公告)号：EP2786520B1
公开(公告)日：2017-09-06
申请号：EP12746397.4
申请日：2012-06-15
申请人： Kabushiki Kaisha Toshiba
发明人： NAGAI, Yuji , SUZUKI, Toshihiro , SHIBATA, Noboru , KATO, Taku , MATSUSHITA, Tatsuyuki
IPC分类号： H04L9/08 , H04L9/32 , G11B20/00
CPC分类号： H04L9/0816 , G11B20/00086 , G11B20/0021 , G11B20/00217 , G11B20/00253 , H04L9/0822 , H04L9/0833 , H04L9/0897 , H04L9/32 , H04L2209/601

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