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1. 发明申请

US20060239057A1 Alignment insensitive D-cache cell 有权
标题翻译：对齐不敏感的D缓存单元
公开(公告)号：US20060239057A1
公开(公告)日：2006-10-26
申请号：US11111454
申请日：2005-04-21
申请人： K. Muller , Kevin Batson , Michael Lee
发明人： K. Muller , Kevin Batson , Michael Lee
IPC分类号： G11C5/06
CPC分类号： G11C11/412 , H01L27/11 , H01L27/1104 , Y10S257/903 , Y10S257/904
摘要： A D-Cache SRAM cell having a modified design in schematic and layout that exhibits increased symmetry from the circuit schematic and the physical cell layout perspectives. That is, the SRAM cell includes two read ports and minimizes asymmetry by provisioning one read port on a true side and one on the complement side. Asymmetry is additionally minimized in layout as cross coupling on both the true and complement sides rises up one level by providing from the local interconnect level a via connection to a M1 or metallization level. Moreover, the distance between the local interconnect (MC) and the gate conductor structure (PC) has been enlarged and equalized for each of the pFETs in the cross-latched SRAM cell. As a result, the SRAM cell has been rendered insensitive to overlay (local interconnect processing too close) by maximizing this MC-PC distance.
摘要翻译：具有改进的示意图和布局设计的D缓存SRAM单元，其显示出来自电路原理图和物理单元布局视角的增加的对称性。也就是说，SRAM单元包括两个读取端口，并且通过在真实侧提供一个读取端口和在补充端上提供一个读取端口来最小化不对称性。通过从本地互连级别提供通向M1或金属化级别的通孔连接，通过从真实和补偿侧两者的交叉耦合上升到一个级别，不对称性在布局中另外最小化。此外，局部互连（MC）和栅极导体结构（PC）之间的距离已经在交叉锁存SRAM单元中的每个pFET被放大和均衡。因此，通过最大化这个MC-PC距离，SRAM单元已经对覆盖（局部互连处理太近）变得不敏感。

2. 发明申请

US20080096342A1 CMOS CIRCUITS INCLUDING A PASSIVE ELEMENT HAVING A LOW END RESISTANCE 有权
标题翻译： CMOS电路，包括具有低端电阻的被动元件
公开(公告)号：US20080096342A1
公开(公告)日：2008-04-24
申请号：US11956993
申请日：2007-12-14
申请人： Christopher Sheraw , Alyssa Bonnoit , K. Muller , Werner Rausch
发明人： Christopher Sheraw , Alyssa Bonnoit , K. Muller , Werner Rausch
IPC分类号： H01L21/8238
CPC分类号： H01L27/0629 , H01L21/26506 , H01L28/20 , H01L28/40 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The present invention relates to complementary metal-oxide-semiconductor (CMOS) circuits, as well as methods for forming such CMOS circuits. More specifically, the present invention relates to CMOS circuits that contain passive elements, such as buried resistors, capacitors, diodes, inductors, attenuators, power dividers, and antennas, etc., which are characterized by an end contact resistance of less than 90 ohm-microns. Such a low end resistance can be achieved either by reducing the spacer widths of the passive elements to a range of from about 10 nm to about 30 nm, or by masking the passive elements during a pre-amorphization implantation step, so that the passive elements are essentially free of pre-amorphization implants.
摘要翻译：本发明涉及互补金属氧化物半导体（CMOS）电路，以及用于形成这种CMOS电路的方法。更具体地说，本发明涉及包含诸如埋地电阻器，电容器，二极管，电感器，衰减器，功率分配器和天线等无源元件的CMOS电路，其特征在于端接触电阻小于90欧姆微量元素这样的低端电阻可以通过将无源元件的间隔物宽度减小到约10nm至约30nm的范围，或通过在预非晶化注入步骤期间掩蔽无源元件来实现，使得无源元件基本上没有前非晶化植入物。

3. 发明申请

US20050221543A1 Double gated transistor and method of fabrication 有权
标题翻译：双门控晶体管及其制造方法
公开(公告)号：US20050221543A1
公开(公告)日：2005-10-06
申请号：US11125063
申请日：2005-05-09
申请人： Andres Bryant , Meikei Ieong , K. Muller , Edward Nowak , David Fried , Jed Rankin
发明人： Andres Bryant , Meikei Ieong , K. Muller , Edward Nowak , David Fried , Jed Rankin
IPC分类号： H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/49 , H01L29/78 , H01L29/786 , H01L21/00
CPC分类号： H01L29/4908 , H01L21/823842 , H01L27/092 , H01L29/66795 , H01L29/785
摘要： Accordingly, the present invention provides a double gated transistor and a method for forming the same that results in improved device performance and density. The preferred embodiment of the present invention uses provides a double gated transistor with asymmetric gate doping, where one of the double gates is doped degenerately n-type and the other degenerately p-type. By doping on of the gates n-type, and the other p-type, the threshold voltage of the resulting device is improved. In particular, by asymmetrically doping the two gates, the resulting transistor can, with adequate doping of the body, have a threshold voltage in a range that enables low-voltage CMOS operation. For example, a transistor can be created that has a threshold voltage between 0V and 0.5V for nFETs and between 0 and −0.5V for pFETs.
摘要翻译：因此，本发明提供一种双门控晶体管及其形成方法，其导致改进的器件性能和密度。本发明的优选实施例提供了具有不对称栅极掺杂的双门控晶体管，其中双栅极中的一个被简并掺杂为n型，另一个为简并p型。通过掺杂栅极n型和另一种p型，所得器件的阈值电压得到改善。特别地，通过不对称地掺杂两个栅极，所得到的晶体管可以通过适当掺杂的体，在允许低电压CMOS操作的范围内具有阈值电压。例如，可以产生对于nFET具有在0V和0.5V之间的阈值电压并且对于pFET而言在0和-0.5V之间的晶体管。

4. 发明申请

US20070254438A1 DOUBLE GATED TRANSISTOR AND METHOD OF FABRICATION 有权
标题翻译：双栅极晶体管和制造方法
公开(公告)号：US20070254438A1
公开(公告)日：2007-11-01
申请号：US11774663
申请日：2007-07-09
申请人： Andres Bryant , Meikei Ieong , K. Muller , Edward Nowak , David Fried , Jed Rankin
发明人： Andres Bryant , Meikei Ieong , K. Muller , Edward Nowak , David Fried , Jed Rankin
IPC分类号： H01L21/336
CPC分类号： H01L29/4908 , H01L21/823842 , H01L27/092 , H01L29/66795 , H01L29/785
摘要： A method for forming a transistor. A semiconductor substrate is provided. The semiconductor substrate is patterned to provide a first body edge. A first gate structure of a first fermi level is provided adjacent the first body edge. The semiconductor substrate is patterned to provide a second body edge. The first and second body edges of the semiconductor substrate define a transistor body. A second gate structure of a second fermi level is provided adjacent the second body edge. A substantially uniform dopant concentration density is formed throughout the transistor body.
摘要翻译：一种形成晶体管的方法。提供半导体衬底。图案化半导体衬底以提供第一本体边缘。在第一身体边缘附近提供第一费米能级的第一门结构。图案化半导体衬底以提供第二本体边缘。半导体衬底的第一和第二主体边缘限定晶体管体。在第二身体边缘附近设置第二费米能级的第二门结构。在整个晶体管本体中形成基本均匀的掺杂剂浓度密度。

5. 发明申请

US20070120195A1 CMOS CIRCUITS INCORPORATING PASSIVE ELEMENTS OF LOW CONTACT RESISTANCE, AND METHODS OF FORMING SAME 有权
标题翻译：兼容低接触电阻的被动元件的CMOS电路及其形成方法
公开(公告)号：US20070120195A1
公开(公告)日：2007-05-31
申请号：US11164515
申请日：2005-11-28
申请人： Christopher Sheraw , Alyssa Bonnoit , K. Muller , Werner Rausch
发明人： Christopher Sheraw , Alyssa Bonnoit , K. Muller , Werner Rausch
IPC分类号： H01L29/94 , H01L29/76
CPC分类号： H01L27/0629 , H01L21/26506 , H01L28/20 , H01L28/40 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The present invention relates to complementary metal-oxide-semiconductor (CMOS) circuits, as well as methods for forming such CMOS circuits. More specifically, the present invention relates to CMOS circuits that contain passive elements, such as buried resistors, capacitors, diodes, inductors, attenuators, power dividers, and antennas, etc., which are characterized by an end contact resistance of less than 90 ohm-microns. Such a low end resistance can be achieved either by reducing the spacer widths of the passive elements to a range of from about 10 nm to about 30 nm, or by masking the passive elements during a pre-amorphization implantation step, so that the passive elements are essentially free of pre-amorphization implants.
摘要翻译：本发明涉及互补金属氧化物半导体（CMOS）电路，以及用于形成这种CMOS电路的方法。更具体地说，本发明涉及包含诸如埋地电阻器，电容器，二极管，电感器，衰减器，功率分配器和天线等无源元件的CMOS电路，其特征在于端接触电阻小于90欧姆微量元素这样的低端电阻可以通过将无源元件的间隔物宽度减小到约10nm至约30nm的范围，或通过在预非晶化注入步骤期间掩蔽无源元件来实现，使得无源元件基本上没有前非晶化植入物。

6. 发明申请

US20050287798A1 PREVENTING CAVITATION IN HIGH ASPECT RATIO DIELECTRIC REGIONS OF SEMICONDUCTOR DEVICE 失效
标题翻译：在半导体器件的高比例电介质区域中防止蚀刻
公开(公告)号：US20050287798A1
公开(公告)日：2005-12-29
申请号：US10710227
申请日：2004-06-28
申请人： Paul Agnello , Rajeev Malik , K. Muller
发明人： Paul Agnello , Rajeev Malik , K. Muller
IPC分类号： H01L21/3205 , H01L21/336 , H01L21/4763 , H01L21/768 , H01L21/8234
CPC分类号： H01L21/76832 , H01L21/76834 , H01L21/76837 , H01L21/823425 , H01L21/823468 , H01L21/823475
摘要： Methods for preventing cavitation in high aspect ratio dielectric regions in a semiconductor device, and the device so formed, are disclosed. The invention includes depositing a first dielectric in the high aspect ratio dielectric region between a pair of structures, and then removing the first dielectric to form a bearing surface adjacent each structure. The bearing surface prevents cavitation of the interlayer dielectric that subsequently fills the high aspect ratio region.
摘要翻译：公开了用于防止在半导体器件中的高纵横比介电区域中的空化的方法以及如此形成的器件。本发明包括在一对结构之间的高纵横比电介质区域中沉积第一电介质，然后移除第一电介质以形成邻近每个结构的支承表面。轴承表面防止随后填充高纵横比区域的层间电介质的空化。

7. 发明申请

US20050121676A1 FinFET SRAM cell using low mobility plane for cell stability and method for forming 失效
标题翻译： FinFET SRAM单元使用低迁移率平面进行电池稳定性和成型方法
公开(公告)号：US20050121676A1
公开(公告)日：2005-06-09
申请号：US10987532
申请日：2004-11-12
申请人： David Fried , Randy Mann , K. Muller , Edward Nowak
发明人： David Fried , Randy Mann , K. Muller , Edward Nowak
IPC分类号： H01L21/8244 , H01L21/84 , H01L27/12 , H01L29/76
CPC分类号： H01L27/11 , H01L21/84 , H01L27/1203 , H01L29/785 , Y10S257/903
摘要： The present invention provides a device design and method for forming the same that results in Fin Field Effect Transistors having different gains without negatively impacting device density. The present invention forms relatively low gain FinFET transistors in a low carrier mobility plane and relatively high gain FinFET transistors in a high carrier mobility plane. Thus formed, the FinFETs formed in the high mobility plane have a relatively higher gain than the FinFETs formed in the low mobility plane. The embodiments are of particular application to the design and fabrication of a Static Random Access Memory (SRAM) cell. In this application, the bodies of the n-type FinFETs used as transfer devices are formed along the {110} plane. The bodies of the n-type FinFETs and p-type FinFETs used as the storage latch are formed along the {100}. Thus formed, the transfer devices will have a gain approximately half that of the n-type storage latch devices, facilitating proper SRAM operation
摘要翻译：本发明提供了一种用于形成它的器件设计和方法，其导致Fin场效应晶体管具有不同的增益而不会不利地影响器件密度。本发明在低载流子迁移率平面中形成相对较低的增益FinFET晶体管，并在高载流子迁移率平面内形成相对较高的增益FinFET晶体管。如此形成的，在高迁移率平面中形成的FinFET具有比在低迁移率平面中形成的FinFET更高的增益。这些实施例特别适用于静态随机存取存储器（SRAM）单元的设计和制造。在这种应用中，用作转移装置的n型FinFET的主体沿{110}平面形成。用作存储锁存器的n型FinFET和p型FinFET的主体沿{100}形成。如此形成的，传送装置的增益大约是n型存储锁存装置的增益的一半，有利于适当的SRAM操作

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