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1. 发明申请

US20050144585A1 Method and system for hardware accelerated verification of digital circuit design and its testbench 有权
标题翻译：数字电路设计硬件加速验证方法与系统及其测试台
公开(公告)号：US20050144585A1
公开(公告)日：2005-06-30
申请号：US10972361
申请日：2004-10-26
申请人： Jyotirmoy Daw , Sanjay Gupta , Suresh Krishnamurthy
发明人： Jyotirmoy Daw , Sanjay Gupta , Suresh Krishnamurthy
IPC分类号： G01R31/3183 , G06F17/50
CPC分类号： G06F17/5027 , G01R31/318314
摘要： A system and method is presented for synthesizing both a design under test (DUT) and its test environment (i.e., the testbench for the DUT), into an equivalent structural model suitable for execution on a reconfigurable hardware platform. This may be achieved without any change in the existing verification methodology. Behavioral HDL may be translated into a form that can be executed on a reconfigurable hardware platform. A set of compilation transforms are provided that convert behavioral constructs into RTL constructs that can be directly mapped onto an emulator. Such transforms are provided by introducing the concepts of a behavioral clock and a time advance finite state machine (FSM) that determines simulation time and sequences concurrent computing blocks in the DUT and the testbench.
摘要翻译：提出了一种系统和方法，用于将待测设计（DUT）及其测试环境（即DUT的测试台）合并成适用于可重配置硬件平台上执行的等效结构模型。这可以在现有的验证方法没有任何改变的情况下实现。行为HDL可以被转换成可以在可重新配置的硬件平台上执行的形式。提供了一组编译变换，将行为结构转换为可直接映射到仿真器的RTL结构。通过引入行为时钟和时间推进有限状态机（FSM）的概念来提供这种变换，该时间预测有限状态机（FSM）确定DUT和测试平台中的模拟时间和序列并发计算块。

2. 发明授权

US07257802B2 Method and system for hardware accelerated verification of digital circuit design and its testbench 有权
标题翻译：数字电路设计硬件加速验证方法与系统及其测试台
公开(公告)号：US07257802B2
公开(公告)日：2007-08-14
申请号：US10972361
申请日：2004-10-26
申请人： Jyotirmoy Daw , Sanjay Gupta , Suresh Krishnamurthy
发明人： Jyotirmoy Daw , Sanjay Gupta , Suresh Krishnamurthy
IPC分类号： G06F17/50
CPC分类号： G06F17/5027 , G01R31/318314
摘要： A system and method is presented for synthesizing both a design under test (DUT) and its test environment (i.e., the testbench for the DUT), into an equivalent structural model suitable for execution on a reconfigurable hardware platform. This may be achieved without any change in the existing verification methodology. Behavioral HDL may be translated into a form that can be executed on a reconfigurable hardware platform. A set of compilation transforms are provided that convert behavioral constructs into RTL constructs that can be directly mapped onto an emulator. Such transforms are provided by introducing the concepts of a behavioral clock and a time advance finite state machine (FSM) that determines simulation time and sequences concurrent computing blocks in the DUT and the testbench.
摘要翻译：提出了一种系统和方法，用于将待测设计（DUT）及其测试环境（即DUT的测试台）合并成适用于可重配置硬件平台上执行的等效结构模型。这可以在现有的验证方法没有任何改变的情况下实现。行为HDL可以被转换成可以在可重新配置的硬件平台上执行的形式。提供了一组编译变换，将行为结构转换为可直接映射到仿真器的RTL结构。通过引入行为时钟和时间推进有限状态机（FSM）的概念来提供这种变换，该时间预测有限状态机（FSM）确定DUT和测试平台中的模拟时间和序列并发计算块。

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