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    • 2. 发明申请
    • DYNAMIC CONTROL LOOP FOR SWITCHING REGULATORS
    • 用于切换调节器的动态控制环
    • US20120038340A1
    • 2012-02-16
    • US12856918
    • 2010-08-16
    • Justin SHIAlan ROTHJustin GAITHEREric SOENEN
    • Justin SHIAlan ROTHJustin GAITHEREric SOENEN
    • G05F1/10
    • H02M3/04H02M3/156H02M2001/0032Y02B70/16
    • Some embodiments regard a method of controlling a regulator having an input voltage and an output voltage, comprising: turning on a first driver; determining a duration ratio having a first time period over the first time period and a second time period; the first time period and the second time period indicating a duration when the first driver and a second driver is on, respectively; generating a second voltage level for the reference voltage based on the duration ratio and a ripple voltage that is a difference between a high threshold voltage and a low threshold voltage; turning off the first driver and turning on the second driver based on a relationship between the second voltage level and a voltage level of the output voltage; turning off the second driver when a current flowing through a node of the output voltage reaches a pre-determined level; and generating a change in the first time period based on the duration ratio and a voltage difference between a peak of the output voltage and the high threshold voltage.
    • 一些实施例涉及一种控制具有输入电压和输出电压的调节器的方法,包括:打开第一驱动器; 确定在所述第一时间段和第二时间段内具有第一时间段的持续时间比; 所述第一时间段和所述第二时间段分别指示所述第一驾驶员和所述第二驾驶员开启时的持续时间; 基于持续时间比产生用于参考电压的第二电压电平,以及纹波电压,其是高阈值电压和低阈值电压之间的差; 基于第二电压电平和输出电压的电压电平之间的关系,关闭第一驱动器并接通第二驱动器; 当流过输出电压的节点的电流达到预定电平时,关闭第二驱动器; 以及基于所述持续时间比和所述输出电压的峰值与所述高阈值电压之间的电压差来产生所述第一时间段的变化。
    • 6. 发明申请
    • IDLE TONE SUPPRESSION CIRCUIT
    • 空闲音抑制电路
    • US20130135131A1
    • 2013-05-30
    • US13481990
    • 2012-05-29
    • Chia Liang TaiAlan ROTHEric SOENEN
    • Chia Liang TaiAlan ROTHEric SOENEN
    • H03M3/02
    • G05B11/01G01K7/16G01K15/005G05B15/02H03M3/344H03M3/458
    • A hysteretic digital filter includes a first multi-bit flip-flop having an input for receiving a series of multi-bit sigma-delta ADC codes, a clock input for receiving a clock signal and an output; a second multi-bit flip-flop having an input coupled to the output of the first multi-bit flip-flop, an output for providing an output code of the digital filter, and an input for receiving a latch control signal, the second multi-bit flip-flop latching its input to its output under control of the latch control signal; and a control circuit. The control circuit is configured to selectively provide the latch control signal to trigger latching by the second multi-bit flip-flop dependent on a running comparison of the output code of the digital filter and the value of individual ones of the multi-bit sigma-delta ADC codes from the series of multi-bit sigma-delta ADC codes.
    • 迟滞数字滤波器包括具有用于接收一系列多比特Σ-ΔADC码的输入的第一多位触发器,用于接收时钟信号和输出的时钟输入; 具有耦合到第一多位触发器的输出的输入的第二多位触发器,用于提供数字滤波器的输出码的输出和用于接收锁存控制信号的输入,第二多位触发器 位触发器在锁存控制信号的控制下将其输入锁存到其输出端; 和控制电路。 控制电路被配置为根据数字滤波器的输出代码的运行比较和多比特Σ-位触发器的各个值的选择性地提供锁存控制信号以触发第二多位触发器的锁存, 来自多位Σ-ΔADC代码的Delta ADC代码。
    • 9. 发明申请
    • DIGITAL LOW DROP-OUT REGULATOR
    • 数字低压降稳压器
    • US20140002041A1
    • 2014-01-02
    • US13837973
    • 2013-03-15
    • Eric SOENENAlan ROTH
    • Eric SOENENAlan ROTH
    • G05F1/575
    • G05F1/575
    • A low drop-out regulator circuit includes a control circuit and a switching device. The control circuit has an output node. The switching device has a first terminal coupled with the output node of the control circuit. The switching device is configured to receive an input voltage at a second terminal of the switching device and provide an output voltage at a third terminal of the switching device. The control circuit is configured to provide a digital signal at the output node of the control circuit based on a feedback voltage of the output voltage at the third terminal of the switching device.
    • 低压差稳压器电路包括控制电路和开关装置。 控制电路具有输出节点。 开关装置具有与控制电路的输出节点耦合的第一端子。 开关装置被配置为在开关装置的第二端子处接收输入电压,并在开关装置的第三端提供输出电压。 控制电路被配置为基于开关装置的第三端子处的输出电压的反馈电压在控制电路的输出节点处提供数字信号。