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1. 发明授权

US08032745B2 Authentication of I2C bus transactions 有权
标题翻译： I2C总线事务的认证
公开(公告)号：US08032745B2
公开(公告)日：2011-10-04
申请号：US11312019
申请日：2005-12-20
申请人： Justin Potok Bandholz , Ralph M. Begun , Andrew S. Heinzmann , Fernando A. Lopez
发明人： Justin Potok Bandholz , Ralph M. Begun , Andrew S. Heinzmann , Fernando A. Lopez
IPC分类号： H04L29/06
CPC分类号： G06F21/85 , H04L9/3236
摘要： This invention enables authenticated communications (transactions) to take place on a standard I2C bus without requiring modification of existing I2C devices. Read and write transactions occurring on the bus are authenticated using an Authentication Agent and a shared secret key. In addition to allowing verification of the legitimacy of the transactions, the authentication of the I2C transactions enhances the reliability and serviceability of the bus and devices on the bus by allowing the Baseboard Management Controller (BMC) to quickly determine and pinpoint errors.
摘要翻译：本发明使得能够在标准I2C总线上进行认证通信（事务），而不需要修改现有的I2C设备。总线上发生的读写事务使用认证代理和共享密钥进行身份验证。除了允许验证交易的合法性之外，I2C事务的认证通过允许基板管理控制器（BMC）快速确定和确定错误来增强总线和总线上的设备的可靠性和可维护性。

2. 发明申请

US20080263560A1 STRUCTURE FOR SECURING LEASED RESOURCES ON A COMPUTER 有权
标题翻译：在计算机上保存资源的结构
公开(公告)号：US20080263560A1
公开(公告)日：2008-10-23
申请号：US12165313
申请日：2008-06-30
申请人： JUSTIN P. BANDHOLZ , Ralph M. Begun , Andrew S. Heinzmann , Fernando A. Lopez
发明人： JUSTIN P. BANDHOLZ , Ralph M. Begun , Andrew S. Heinzmann , Fernando A. Lopez
IPC分类号： G06F9/50
CPC分类号： G06F21/57 , G06F2221/2135
摘要： A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is for securing of leased resources on a computer. The design structure includes a computer for securing resources may comprise at least one processor, a plurality of resources, wherein each resource is associated with configuration data and a programmable logic device connected to each of the plurality of resources. The programmable logic device may be configured for determining whether a resource is leased, reading un-encoded configuration data from a resource, and sending the configuration data to a first unit, if the resource is not leased. The programmable logic device may further be configured for reading encoded configuration data from a resource, decoding the configuration data, sending the configuration data that was decoded to a first unit, and logging use of the resource by the first unit, if the resource is leased.
摘要翻译：体现在用于设计，制造和/或测试设计的机器可读存储介质中的设计结构用于确保计算机上的租用资源。设计结构包括用于保护资源的计算机可以包括至少一个处理器，多个资源，其中每个资源与配置数据相关联，以及连接到多个资源中的每一个的可编程逻辑设备。可编程逻辑设备可以被配置为用于确定资源是否租用，从资源读取未编码的配置数据，以及如果所述资源不被租用，则将所述配置数据发送到第一单元。可编程逻辑设备还可以被配置为：如果资源被租赁，则从资源读取编码的配置数据，解码配置数据，将被解码的配置数据发送到第一单元，以及记录第一单元的资源的使用。

3. 发明授权

US08028069B2 Structure for securing leased resources on a computer 有权
标题翻译：用于在计算机上确保租用资源的结构
公开(公告)号：US08028069B2
公开(公告)日：2011-09-27
申请号：US12165313
申请日：2008-06-30
申请人： Justin P. Bandholz , Ralph M. Begun , Andrew S. Heinzmann , Fernando A. Lopez
发明人： Justin P. Bandholz , Ralph M. Begun , Andrew S. Heinzmann , Fernando A. Lopez
IPC分类号： G06F15/173
CPC分类号： G06F21/57 , G06F2221/2135
摘要： A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is for securing of leased resources on a computer. The design structure includes a computer for securing resources may comprise at least one processor, a plurality of resources, wherein each resource is associated with configuration data and a programmable logic device connected to each of the plurality of resources. The programmable logic device may be configured for determining whether a resource is leased, reading un-encoded configuration data from a resource, and sending the configuration data to a first unit, if the resource is not leased. The programmable logic device may further be configured for reading encoded configuration data from a resource, decoding the configuration data, sending the configuration data that was decoded to a first unit, and logging use of the resource by the first unit, if the resource is leased.
摘要翻译：体现在用于设计，制造和/或测试设计的机器可读存储介质中的设计结构用于确保计算机上的租用资源。设计结构包括用于保护资源的计算机可以包括至少一个处理器，多个资源，其中每个资源与配置数据相关联，以及连接到多个资源中的每一个的可编程逻辑设备。可编程逻辑设备可以被配置为用于确定资源是否租用，从资源读取未编码的配置数据，以及如果所述资源不被租用，则将所述配置数据发送到第一单元。可编程逻辑设备还可以被配置为：如果资源被租赁，则从资源读取编码的配置数据，解码配置数据，将被解码的配置数据发送到第一单元，以及记录第一单元的资源的使用。

4. 发明授权

US08819484B2 Dynamically reconfiguring a primary processor identity within a multi-processor socket server 有权
标题翻译：在多处理器套接字服务器内动态重新配置主处理器标识
公开(公告)号：US08819484B2
公开(公告)日：2014-08-26
申请号：US13268068
申请日：2011-10-07
申请人： Ralph M. Begun , Michael Decesaris , Randolph S. Kolvick , Steven L. Vanderlinden
发明人： Ralph M. Begun , Michael Decesaris , Randolph S. Kolvick , Steven L. Vanderlinden
IPC分类号： G06F11/00
CPC分类号： G06F11/1428 , G06F11/0724 , G06F11/0751
摘要： Methods, apparatuses, and computer program products for dynamically reconfiguring a primary processor identity within a multi-processor socket server are provided. Embodiments include detecting, by the service processor, a processor socket reconfiguration event corresponding to a first processor socket; disabling, by the service processor, the first processor socket of the server in response to detecting the processor socket reconfiguration event; and reassigning, by the service processor, the primary processor identity to a second processor socket of the server.
摘要翻译：提供了用于在多处理器插座服务器内动态地重新配置主处理器标识的方法，装置和计算机程序产品。实施例包括由服务处理器检测对应于第一处理器插座的处理器插座重新配置事件; 响应于检测到处理器插座重新配置事件，由服务处理器禁用服务器的第一处理器插槽; 以及由所述服务处理器将所述主处理器标识重新分配给所述服务器的第二处理器插槽。

5. 发明申请

US20130091380A1 Dynamically Reconfiguring A Primary Processor Identity Within A Multi-Processor Socket Server 有权
标题翻译：在多处理器套接字服务器中动态重新配置主处理器标识
公开(公告)号：US20130091380A1
公开(公告)日：2013-04-11
申请号：US13268068
申请日：2011-10-07
申请人： Michael Decesaris , Ralph M. Begun , Randolph S. Kolvick , Steven L. Vanderlinden
发明人： Michael Decesaris , Ralph M. Begun , Randolph S. Kolvick , Steven L. Vanderlinden
IPC分类号： G06F15/76 , G06F9/02 , G06F11/20
CPC分类号： G06F11/1428 , G06F11/0724 , G06F11/0751
摘要： Methods, apparatuses, and computer program products for dynamically reconfiguring a primary processor identity within a multi-processor socket server are provided. Embodiments include detecting, by the service processor, a processor socket reconfiguration event corresponding to a first processor socket; disabling, by the service processor, the first processor socket of the server in response to detecting the processor socket reconfiguration event; and reassigning, by the service processor, the primary processor identity to a second processor socket of the server.
摘要翻译：提供了用于在多处理器插座服务器内动态地重新配置主处理器标识的方法，装置和计算机程序产品。实施例包括由服务处理器检测对应于第一处理器插座的处理器插座重新配置事件; 响应于检测到处理器插座重新配置事件，由服务处理器禁用服务器的第一处理器插槽; 以及由所述服务处理器将所述主处理器标识重新分配给所述服务器的第二处理器插槽。

6. 发明授权

US5170481A Microprocessor hold and lock circuitry 失效
标题翻译：微处理器保持和锁定电路
公开(公告)号：US5170481A
公开(公告)日：1992-12-08
申请号：US367828
申请日：1989-06-19
申请人： Ralph M. Begun , Patrick M. Bland , Mark E. Dean
发明人： Ralph M. Begun , Patrick M. Bland , Mark E. Dean
IPC分类号： G06F13/36 , G06F13/28 , G06F13/362
CPC分类号： G06F13/285 , G06F13/362
摘要： A logic circit external to a microprocessor monitors selected processor I/O pins to determine the current processor cycle and, in response to a hold request signal, drives the processor into a hold state at the appropriate time in the cycle. The logic circuit also includes a "lockbus" feature that, when the processor is not idle, "locks" the microprocessor to the local CPU bus for a predetermined period of time immediately after the processor is released from a hold state.

7. 发明授权

US5459842A System for combining data from multiple CPU write requests via buffers and using read-modify-write operation to write the combined data to the memory 失效
标题翻译：用于通过缓冲区组合来自多个CPU写请求的数据并使用读 - 修改 - 写操作将组合数据写入存储器的系统
公开(公告)号：US5459842A
公开(公告)日：1995-10-17
申请号：US905259
申请日：1992-06-26
申请人： Ralph M. Begun , Paul W. Browne , Marc R. Faucher , Gerald L. Frank , Christopher M. Herring
发明人： Ralph M. Begun , Paul W. Browne , Marc R. Faucher , Gerald L. Frank , Christopher M. Herring
IPC分类号： G06F12/00 , B82B1/00 , G06F9/38 , G06F12/04 , G06F13/16 , G06F13/38 , G06F13/14
CPC分类号： G06F13/1631
摘要： A write compression buffer is connected to a CPU bus and to a memory controller to provide write cycle compression in which plural partial write requests to the same memory address are compressed into a single memory write cycle. The buffer has a plurality of buffering level.
摘要翻译：写压缩缓冲器连接到CPU总线和存储器控制器以提供写周期压缩，其中对相同存储器地址的多个部分写请求被压缩为单个存储器写周期。缓冲器具有多个缓冲级别。

8. 发明授权

US5182809A Dual bus microcomputer system with programmable control of lock function 失效
标题翻译：具有可编程锁定功能的双总线微型计算机系统
公开(公告)号：US5182809A
公开(公告)日：1993-01-26
申请号：US358810
申请日：1989-05-31
申请人： Ralph M. Begun , Patrick M. Bland , Philip E. Milling
发明人： Ralph M. Begun , Patrick M. Bland , Philip E. Milling
IPC分类号： G06F12/08
CPC分类号： G06F12/0888
摘要： A dual bus microcomputer system including a cache subsystem improves performance under certain circumstances by allowing programmable control over the LOCK function. More particularly, additional logic is coupled between the LOCK output of the CPU and the LOCK input of the cache controller. A control bit from an I/O port is a second input to the additional logic. With the control bit in one state, the logic allows the LOCK input to follow the LOCK output. In the other state of the control bit, the LOCK input is disabled regardless of the state of the LOCK output.

9. 发明授权

US5045998A Method and apparatus for selectively posting write cycles using the 82385 cache controller 失效
标题翻译：使用82385高速缓存控制器选择性地发布写周期的方法和装置
公开(公告)号：US5045998A
公开(公告)日：1991-09-03
申请号：US359794
申请日：1989-06-01
申请人： Ralph M. Begun , Patrick M. Bland , Mark E. Dean
发明人： Ralph M. Begun , Patrick M. Bland , Mark E. Dean
IPC分类号： G06F12/08
CPC分类号： G06F12/0888
摘要： A microprocessor system employing an 80386 CPU and an 82385 cache controller has the capability of functioning with dynamic bus sizing (where the CPU interacts with devices which may or may not be 32-bits wide), as well as posted write capability. Unfortunately, the two capabilities have the possibility of an incompatibility if a write cycle is posted to a device which cannot transfer 32 bits on a single cycle. The present invention provides logic to overcome this incompatibility. An address decoder is provided to decode the tag portion of an address asserted on a CPU bus to determine if the asserted address is inside or outside a range of addresses which define cacheable devices. Any cacheable device is by definition 32 bits wide and therefore posted writes are allowed only to cacheable devices. Accordingly, the microcomputer system employing the invention posts write cycles to cacheable devices; write cycles to non-cacheable devices are inhibited from being posted.
摘要翻译：采用80386 CPU和82385高速缓存控制器的微处理器系统具有动态总线大小调整功能（CPU与可能或不是32位宽的设备交互）以及发布的写入功能。不幸的是，如果将写周期发布到在单个周期内不能传输32位的器件，则这两个功能具有不兼容的可能性。本发明提供了克服这种不兼容性的逻辑。提供地址解码器来解码在CPU总线上断言的地址的标签部分，以确定所断言的地址是否在限定可高速缓存设备的地址范围之内或之外。任何可缓存设备的定义为32位宽，因此发布的写入仅允许可缓存设备。因此，采用本发明的微计算机系统将写入周期写入可高速缓存的设备; 对不可缓存设备的写周期被禁止发布。

10. 发明授权

US07487222B2 System management architecture for multi-node computer system 失效
标题翻译：多节点计算机系统的系统管理架构
公开(公告)号：US07487222B2
公开(公告)日：2009-02-03
申请号：US11092188
申请日：2005-03-29
申请人： Ralph M. Begun , Adam L. Soderlund
发明人： Ralph M. Begun , Adam L. Soderlund
IPC分类号： G06F15/173
CPC分类号： G06F15/16
摘要： In a multi-node SMP system, at least one processor per node is enabled to execute the SMM task for the hardware resources that are local to that node. Additionally, each node is allocated its own local SMM code copy in its own SMM memory segment, to allow for improved access and a further reduction in internode traffic. In a preferred embodiment, only a signle processor per node is enabled to execute the SMM tasks, and specific SMM memory locations within the SMM memory segments are allocated and used to report status and results from each node. A root node SMM processor monitors the SMM status entries of the other nodes for completion. To further reduce run-time internode traffic, a per-node resource map is created to identify memory and I/O resources that are specific to a particular node. This per-node resource map is then stored locally within the SMM space on each node, respectively.
摘要翻译：在多节点SMP系统中，每个节点至少有一个处理器能够为该节点本地的硬件资源执行SMM任务。另外，每个节点在其自己的SMM存储器段中分配其自己的本地SMM代码副本，以允许改进的访问和节点内流量的进一步减少。在优选实施例中，仅每个节点的签名处理器能够执行SMM任务，并且分配SMM存储器段内的特定SMM存储器位置并用于报告来自每个节点的状态和结果。根节点SMM处理器监视其他节点的SMM状态条目以完成。为了进一步减少运行时节点间流量，创建了每节点资源映射，以识别特定于特定节点的内存和I / O资源。然后将该每节点资源映射分别存储在每个节点上的SMM空间内。

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