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1. 发明申请

US20080176366A1 Method for fabricating AIGaN/GaN-HEMT using selective regrowth 审中-公开
标题翻译：使用选择性再生长制造AIGaN / GaN-HEMT的方法
公开(公告)号：US20080176366A1
公开(公告)日：2008-07-24
申请号：US11984015
申请日：2007-11-13
申请人： Juro Mita , Fumihiko Toda , Toshiharu Marui
发明人： Juro Mita , Fumihiko Toda , Toshiharu Marui
IPC分类号： H01L21/338
CPC分类号： H01L29/7786 , H01L29/2003 , H01L29/42316 , H01L29/66462
摘要： A semiconductor body includes, on a substrate, a stack of buffer layer, UID-GaN layer overlying the buffer layer, and UID-AlGaN layer overlying the UID-GaN layer. On the surface of the UID-AlGaN layer, an insulation film is deposited and patterned. An n+-GaN layer is selectively regrown directly on a region of the surface of the semiconductor body other than the insulation film using the patterned insulation film as a mask without etching the surface of the semiconductor body. A portion of the selectively regrown n+-GaN layer corresponding to a region reserved for an ohmic contact electrode is defined and the ohmic contact electrode is formed on the region. An opening exposing a region reserved for a gate electrode is defined and formed within the insulation SiO2 layer, and a gate electrode is formed in the region. An AlGaN/GaN-HEMT or MIS type of AlGaN/GaN-HEMT has lower contact resistance and uniform device characteristics.
摘要翻译：半导体本体在衬底上包括一叠缓冲层，覆盖缓冲层的UID-GaN层和覆盖在UID-GaN层上的UID-AlGaN层。在UID-AlGaN层的表面上，淀积并图案化绝缘膜。在不蚀刻半导体本体的表面的情况下，使用图案化的绝缘膜作为掩模，在半导体本体的除了绝缘膜之外的区域的区域上选择性地重新生长n + SUP / GaN。限定与欧姆接触电极保留的区域对应的部分选择性再生长的n + S + GaN层，并且在该区域上形成欧姆接触电极。在绝缘SiO 2层内限定并形成露出用于栅电极的区域的开口，并且在该区域中形成栅电极。 AlGaN / GaN-HEMT或MIS型AlGaN / GaN-HEMT具有较低的接触电阻和均匀的器件特性。

2. 发明授权

US07763910B2 Semiconductor device and manufacturing method 有权
标题翻译：半导体器件及制造方法
公开(公告)号：US07763910B2
公开(公告)日：2010-07-27
申请号：US12382664
申请日：2009-03-20
申请人： Toshiharu Marui , Fumihiko Toda , Shinichi Hoshi
发明人： Toshiharu Marui , Fumihiko Toda , Shinichi Hoshi
IPC分类号： H01L29/778
CPC分类号： H01L29/7786 , H01L29/402 , H01L29/42316 , H01L29/66462
摘要： A semiconductor device has source and drain electrodes formed on a substrate, a gate insulation film formed on the substrate between the source and drain electrodes, and a gate electrode formed on the gate insulation film. These elements are all covered by a dielectric sub-insulation film. An opening is formed in the sub-insulation film, partially exposing the gate electrode. A field plate extends from the top of the gate electrode down one side of the gate electrode as far as the sub-insulation film covering the gate insulation film, filling the opening. The thickness of the sub-insulation film can be selected to optimize the separation between the field plate and the substrate for the purpose of reducing current collapse by reducing electric field concentration at the edge of the gate electrode.
摘要翻译：半导体器件具有形成在基板上的源极和漏极，在源极和漏极之间的基板上形成的栅极绝缘膜，以及形成在栅极绝缘膜上的栅电极。这些元件都被绝缘子绝缘膜覆盖。在副绝缘膜中形成开口，部分地露出栅电极。场板从栅电极的顶部向下延伸到栅电极的一侧，直到覆盖栅绝缘膜的次绝缘膜填充开口。可以选择次级绝缘膜的厚度以优化场板和衬底之间的分离，以便通过降低栅电极边缘处的电场浓度来减少电流崩塌。

3. 发明申请

US20100258845A1 Semiconductor device and method for manufacturing same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20100258845A1
公开(公告)日：2010-10-14
申请号：US12659336
申请日：2010-03-04
申请人： Toshiharu Marui , Fumihiko Toda
发明人： Toshiharu Marui , Fumihiko Toda
IPC分类号： H01L29/778 , H01L21/20
CPC分类号： H01L21/0254 , H01L21/02381 , H01L21/02458 , H01L21/02463 , H01L21/02507 , H01L21/02546 , H01L21/02579 , H01L29/155 , H01L29/2003 , H01L29/7787
摘要： There is provided a semiconductor device capable of deactivating 2-dimensional electron gas (2DEG) layers in a buffer layer having a multi-layer film structure. The buffer layer is formed in a high electron mobility transistor (HEMT) formed on a silicon (Si) substrate. The semiconductor device includes the substrate whose uppermost layer is the Si layer, the buffer layer constructed by alternately stacking a plurality of first layers and a plurality of second layers on the Si layer, third layer serving as an electron transit layer formed on the buffer layer, and fourth layer serving as an electron supplying layer formed on the third layer. The first layer is composed of the same material as for the third layer. A p-type impurity is introduced into the first layers so as to deactivate the 2DEG layers formed in the first layer near interfaces between the first and second layers.
摘要翻译：提供了能够使具有多层膜结构的缓冲层中的二维电子气（2DEG）层失活的半导体器件。缓冲层形成在形成在硅（Si）衬底上的高电子迁移率晶体管（HEMT）中。半导体器件包括其最上层为Si层的衬底，通过在Si层上交替堆叠多个第一层和多个第二层而构成的缓冲层，用作形成在缓冲层上的电子迁移层的第三层以及用作形成在第三层上的电子供给层的第四层。第一层由与第三层相同的材料组成。 p型杂质被引入到第一层中，以使在第一层和第二层之间的界面附近形成在第一层中的2DEG层失活。

4. 发明申请

US20090242937A1 Semiconductor device and manufacturing method 有权
标题翻译：半导体器件及制造方法
公开(公告)号：US20090242937A1
公开(公告)日：2009-10-01
申请号：US12382664
申请日：2009-03-20
申请人： Toshiharu Marui , Fumihiko Toda , Shinichi Hoshi
发明人： Toshiharu Marui , Fumihiko Toda , Shinichi Hoshi
IPC分类号： H01L29/778 , H01L21/336
CPC分类号： H01L29/7786 , H01L29/402 , H01L29/42316 , H01L29/66462
摘要： A semiconductor device has source and drain electrodes formed on a substrate, a gate insulation film formed on the substrate between the source and drain electrodes, and a gate electrode formed on the gate insulation film. These elements are all covered by a dielectric sub-insulation film. An opening is formed in the sub-insulation film, partially exposing the gate electrode. A field plate extends from the top of the gate electrode down one side of the gate electrode as far as the sub-insulation film covering the gate insulation film, filling the opening. The thickness of the sub-insulation film can be selected to optimize the separation between the field plate and the substrate for the purpose of reducing current collapse by reducing electric field concentration at the edge of the gate electrode.
摘要翻译：半导体器件具有形成在基板上的源极和漏极，在源极和漏极之间的基板上形成的栅极绝缘膜，以及形成在栅极绝缘膜上的栅电极。这些元件都被绝缘子绝缘膜覆盖。在副绝缘膜中形成开口，部分地露出栅电极。场板从栅电极的顶部向下延伸到栅电极的一侧，直到覆盖栅绝缘膜的次绝缘膜填充开口。可以选择次级绝缘膜的厚度以优化场板和衬底之间的分离，以便通过降低栅电极边缘处的电场浓度来减少电流崩塌。

5. 发明申请

US20090001381A1 Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20090001381A1
公开(公告)日：2009-01-01
申请号：US12153953
申请日：2008-05-28
申请人： Toshiharu Marui , Hideyuki Okita , Shinichi Hoshi , Fumihiko Toda
发明人： Toshiharu Marui , Hideyuki Okita , Shinichi Hoshi , Fumihiko Toda
IPC分类号： H01L29/778
CPC分类号： H01L29/0653 , H01L29/2003 , H01L29/66462 , H01L29/7787
摘要： A semiconductor device includes a substrate, laminated layers provided on the substrate. The laminated layers include an AlGaN barrier layer as an uppermost layer. A gate electrode is provided in a channel region of the laminated layers. A source electrode and a drain electrode are provided so as to face each other via the channel region interposed therebetween. A silicon nitride film is formed to cover an exposed surface of the laminated layers exposed via the gate electrode, the source electrode and the drain electrode. The silicon nitride film has characteristics that an etching rate thereof is in a range from 1 nm per/min to 2 nm/min for an etchant in which hydrofluoric acid having a concentration of 50 weight percent and ammonium fluoride having a concentration of 40 weight percent are mixed at a mixing ratio of 1:9.
摘要翻译：半导体器件包括衬底，设置在衬底上的层叠层。层叠层包括作为最上层的AlGaN阻挡层。栅电极设置在层叠层的沟道区域中。源电极和漏电极经由插入其间的沟道区域彼此面对地设置。形成氮化硅膜以覆盖经由栅电极，源电极和漏电极露出的层叠层的暴露表面。氮化硅膜的特征在于，对于浓度为50重量％的氢氟酸和浓度为40重量％的氟化铵的蚀刻剂，其蚀刻速率在1nm / min〜2nm / min的范围内以1:9的混合比混合。

6. 发明授权

US08114726B2 AlGaN/GaN HEMT with normally-off threshold minimized and method of manufacturing the same 有权
标题翻译：具有常关阈值的AlGaN / GaN HEMT最小化及其制造方法
公开(公告)号：US08114726B2
公开(公告)日：2012-02-14
申请号：US12923550
申请日：2010-09-28
申请人： Toshiharu Marui , Hideyuki Okita
发明人： Toshiharu Marui , Hideyuki Okita
IPC分类号： H01L21/336
CPC分类号： H01L29/7787 , H01L29/2003 , H01L29/42316 , H01L29/66462
摘要： In a method of forming a gate recess, on a surface of an epitaxial wafer including an epitaxial substrate, having a semiconductor layer having the band gap energy varying therein in the depth-wise direction, and a SiN surface protective layer, having a sidewall forming a gate opening and coating the surface of the epitaxial substrate, ultraviolet light having its energy equivalent to the band gap energy of the specific semiconductor layer is irradiated, while the specific semiconductor layer is photoelectrochemically etched from the gate opening with the SiN surface protective layer used as a mask. The gate recess free from plasma ion-induced damage is thus obtained.
摘要翻译：在形成栅极凹部的方法中，在包括外延基板的外延晶片的表面上，具有在深度方向上具有带隙能量变化的半导体层和SiN表面保护层，其具有侧壁形成开口并涂覆外延基板的表面，照射具有与特定半导体层的带隙能量相当的能量的紫外光，同时使用SiN表面保护层从栅极开口光电化学蚀刻特定半导体层作为面具。因此获得了没有等离子体离子诱导的损伤的栅极凹槽。

7. 发明申请

US20080272443A1 Field effect transistor having field plate electrodes 审中-公开
标题翻译：具有场板电极的场效应晶体管
公开(公告)号：US20080272443A1
公开(公告)日：2008-11-06
申请号：US12149325
申请日：2008-04-30
申请人： Shinichi Hoshi , Masanori Itoh , Hideyuki Okita , Toshiharu Marui
发明人： Shinichi Hoshi , Masanori Itoh , Hideyuki Okita , Toshiharu Marui
IPC分类号： H01L29/78 , H01L29/778
CPC分类号： H01L29/402 , H01L29/0692 , H01L29/2003 , H01L29/404 , H01L29/42316 , H01L29/7783 , H01L29/78 , H01L29/812
摘要： A field effect transistor includes an active layer formed on a semiconductor substrate, source and drain electrodes formed apart from each other on the active layer, a gate electrode formed between the source and drain electrodes, a first interlayer film formed on the active layer, a first field plate (FP) electrode connected to the gate electrode and provided on the first interlayer film between the gate and drain electrodes, a second interlayer film formed on the first interlayer film, and a second FP electrode connected to the source electrode and provided on the second interlayer film between the first FP and drain electrodes. The field effect transistor is provided which exhibits a comparatively high gain factor at high frequencies.
摘要翻译：场效应晶体管包括形成在半导体衬底上的有源层，在有源层上彼此分开形成的源极和漏极，形成在源极和漏极之间的栅极，形成在有源层上的第一层间膜，第一场板（FP）电极，连接到栅电极并设置在栅极和漏极之间的第一层间膜上，形成在第一层间膜上的第二层间膜和连接到源极的第二FP电极，在第一FP和漏电极之间的第二层间膜。提供了在高频下表现出较高增益系数的场效应晶体管。

8. 发明申请

US20080283844A1 Method for manufacturing a field effect transistor having a field plate 有权
标题翻译：具有场板的场效应晶体管的制造方法
公开(公告)号：US20080283844A1
公开(公告)日：2008-11-20
申请号：US12149823
申请日：2008-05-08
申请人： Shinichi Hoshi , Masanori Itoh , Hideyuki Okita , Toshiharu Marui
发明人： Shinichi Hoshi , Masanori Itoh , Hideyuki Okita , Toshiharu Marui
IPC分类号： H01L29/778 , H01L21/338
CPC分类号： H01L29/42316 , H01L29/2003 , H01L29/402 , H01L29/66462 , H01L29/7787
摘要： An opening for forming a gate electrode is provided by a first photoresist pattern formed on an insulating film. Reactive ion etching by inductively coupled plasma is applied to the insulating film through the first photoresist pattern as a mask to thereby expose the surface of a GaN semiconductor layer, evaporating thereon a gate metal such as NiAu, thereby forming the gate electrode by self-aligned process. This prevents an oxidized film from being formed on the surface of the semiconductor layer. After the gate electrode is formed, a second photoresist pattern is formed to form a field plate on the gate electrode and the insulating film through the second photoresist pattern as a mask. Thereby, Ti having a high adhesiveness with an insulating film made of SiN or the like can be used as a field plate metal.
摘要翻译：用于形成栅电极的开口由形成在绝缘膜上的第一光致抗蚀剂图案提供。通过电感耦合等离子体的反应离子蚀刻通过第一光致抗蚀剂图案作为掩模施加到绝缘膜，从而暴露GaN半导体层的表面，在其上蒸发诸如NiAu的栅极金属，由此通过自对准形成栅极电极处理。这防止在半导体层的表面上形成氧化膜。在形成栅电极之后，形成第二光致抗蚀剂图案，以通过第二光致抗蚀剂图案作为掩模在栅电极和绝缘膜上形成场板。由此，可以使用与由SiN等制成的绝缘膜具有高粘接性的Ti作为场板金属。

9. 发明申请

US20110073912A1 AlGaN/GaN hemt with normally-off threshold minimized and method of manufacturing the same 有权
标题翻译：具有常关阈值的AlGaN / GaN半导体最小化及其制造方法
公开(公告)号：US20110073912A1
公开(公告)日：2011-03-31
申请号：US12923550
申请日：2010-09-28
申请人： Toshiharu Marui , Hideyuki Okita
发明人： Toshiharu Marui , Hideyuki Okita
IPC分类号： H01L29/737 , H01L21/20
CPC分类号： H01L29/7787 , H01L29/2003 , H01L29/42316 , H01L29/66462
摘要： In a method of forming a gate recess, on a surface of an epitaxial wafer including an epitaxial substrate, having a semiconductor layer having the band gap energy varying therein in the depth-wise direction, and a SiN surface protective layer, having a sidewall forming a gate opening and coating the surface of the epitaxial substrate, ultraviolet light having its energy equivalent to the band gap energy of the specific semiconductor layer is irradiated, while the specific semiconductor layer is photoelectrochemically etched from the gate opening with the SiN surface protective layer used as a mask. The gate recess free from plasma ion-induced damage is thus obtained.
摘要翻译：在形成栅极凹部的方法中，在包括外延基板的外延晶片的表面上，具有在深度方向上具有带隙能量变化的半导体层和SiN表面保护层，其具有侧壁形成开口并涂覆外延基板的表面，照射具有与特定半导体层的带隙能量相当的能量的紫外光，同时使用SiN表面保护层从栅极开口光电化学蚀刻特定半导体层作为面具。因此获得了没有等离子体离子诱导的损伤的栅极凹槽。

10. 发明授权

US07811872B2 Method for manufacturing a field effect transistor having a field plate 有权
标题翻译：具有场板的场效应晶体管的制造方法
公开(公告)号：US07811872B2
公开(公告)日：2010-10-12
申请号：US12149823
申请日：2008-05-08
申请人： Shinichi Hoshi , Masanori Itoh , Hideyuki Okita , Toshiharu Marui
发明人： Shinichi Hoshi , Masanori Itoh , Hideyuki Okita , Toshiharu Marui
IPC分类号： H01L21/338
CPC分类号： H01L29/42316 , H01L29/2003 , H01L29/402 , H01L29/66462 , H01L29/7787
摘要： An opening for forming a gate electrode is provided by a first photoresist pattern formed on an insulating film. Reactive ion etching by inductively coupled plasma is applied to the insulating film through the first photoresist pattern as a mask to thereby expose the surface of a GaN semiconductor layer, evaporating thereon a gate metal such as NiAu, thereby forming the gate electrode by self-aligned process. This prevents an oxidized film from being formed on the surface of the semiconductor layer. After the gate electrode is formed, a second photoresist pattern is formed to form a field plate on the gate electrode and the insulating film through the second photoresist pattern as a mask. Thereby, Ti having a high adhesiveness with an insulating film made of SiN or the like can be used as a field plate metal.
摘要翻译：用于形成栅电极的开口由形成在绝缘膜上的第一光致抗蚀剂图案提供。通过电感耦合等离子体的反应离子蚀刻通过第一光致抗蚀剂图案作为掩模施加到绝缘膜，从而暴露GaN半导体层的表面，在其上蒸发诸如NiAu的栅极金属，由此通过自对准形成栅极电极处理。这防止在半导体层的表面上形成氧化膜。在形成栅电极之后，形成第二光致抗蚀剂图案，以通过第二光致抗蚀剂图案作为掩模在栅电极和绝缘膜上形成场板。由此，可以使用与由SiN等制成的绝缘膜具有高粘接性的Ti作为场板金属。

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