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1. 发明申请

US20090098701A1 Method of manufacturing an integrated circuit 审中-公开
标题翻译：集成电路的制造方法
公开(公告)号：US20090098701A1
公开(公告)日：2009-04-16
申请号：US11974570
申请日：2007-10-15
申请人： Jurgen Faul , Martin Popp , Andrew Graham , Dongping Wu , Victor Verdugo
发明人： Jurgen Faul , Martin Popp , Andrew Graham , Dongping Wu , Victor Verdugo
IPC分类号： H01L21/336
CPC分类号： H01L21/26506 , H01L27/10876 , H01L29/4236 , H01L29/66621
摘要： The present invention provides a method of manufacturing an integrated circuit comprising the steps of: providing a semiconductor substrate, etching at least one trench into a surface of said semiconductor substrate, performing an ion implantation step, wherein a direction of said ion implantation step is parallel to a vertical centre line of said trench, and performing a single oxidation step to form a first oxide layer with a first layer thickness covering a bottom of said at least one trench and a second oxide layer with a second layer thickness covering the sidewalls of said at least one trench, wherein said first layer thickness differs from said second layer thickness.
摘要翻译：本发明提供一种制造集成电路的方法，包括以下步骤：提供半导体衬底，将至少一个沟槽蚀刻到所述半导体衬底的表面中，执行离子注入步骤，其中所述离子注入步骤的方向是平行的到所述沟槽的垂直中心线，并且执行单个氧化步骤以形成覆盖所述至少一个沟槽的底部的第一层厚度的第一氧化物层和覆盖所述至少一个沟槽的侧壁的第二层厚度的第二氧化物层至少一个沟槽，其中所述第一层厚度与所述第二层厚度不同。

2. 发明申请

US20090057810A1 Method of Fabricating an Integrated Circuit 审中-公开
标题翻译：制造集成电路的方法
公开(公告)号：US20090057810A1
公开(公告)日：2009-03-05
申请号：US11850440
申请日：2007-09-05
申请人： Victor Verdugo , Dongping Wu , Clemens Fitz
发明人： Victor Verdugo , Dongping Wu , Clemens Fitz
IPC分类号： H01L21/8242 , H01L29/02
CPC分类号： H01L27/10894 , H01L27/10876
摘要： A method of fabricating an integrated circuit includes providing a semiconductor substrate having a doped area; generating a conductive structure towards the doped area, wherein the conductive structure includes an extending section that protrudes from the doped area; generating an electrically isolating layer at a sidewall of the extending section after generating the conductive structure.
摘要翻译：一种制造集成电路的方法包括：提供具有掺杂区域的半导体衬底; 向所述掺杂区域产生导电结构，其中所述导电结构包括从所述掺杂区域突出的延伸部分; 在产生导电结构之后，在延伸部分的侧壁处产生电绝缘层。

3. 发明申请

US20160190293A1 A Transistor and Method of Making 有权
标题翻译：晶体管及其制作方法
公开(公告)号：US20160190293A1
公开(公告)日：2016-06-30
申请号：US13704613
申请日：2012-12-14
申请人： Dongping Wu , Chaochao Fu , Wei Zhang , Shili Zhang
发明人： Dongping Wu , Chaochao Fu , Wei Zhang , Shili Zhang
IPC分类号： H01L29/737 , H01L29/08 , H01L29/165 , H01L21/285 , H01L29/45 , H01L29/417 , H01L29/66 , H01L21/02 , H01L29/10 , H01L29/167
CPC分类号： H01L29/7378 , H01L21/02532 , H01L21/0257 , H01L21/02598 , H01L21/0262 , H01L21/28518 , H01L21/2855 , H01L29/0817 , H01L29/0821 , H01L29/1004 , H01L29/165 , H01L29/167 , H01L29/41708 , H01L29/456 , H01L29/66242 , H01L29/7371
摘要： A SiGe HBT has an inverted heterojunction structure, where the emitter layer is formed prior to the base layer and the collector layer. The frequency performance of the SiGe HBT is significantly improved through a better thermal process budget for the base profile, essential for higher cut-off frequency (fT) and a minimal collector-base area for a reduced parasitic capacitance, essential for higher maximum oscillation frequency (fmax). This inverted heterojunction structure can be fabricated by using ALE processes to form an emitter on a preformed epitaxial silicide, a base over the emitter and a collector over the base.
摘要翻译： SiGe HBT具有反相异质结结构，其中发射极层在基极层和集电极层之前形成。 SiGe HBT的频率性能通过基底轮廓的更好的热处理预算得到显着改善，对于较高的截止频率（fT）和减少的寄生电容的最小集电极基极面积是必不可少的，因为较高的最大振荡频率（fmax）。该反转异质结结构可以通过使用ALE工艺在预制的外延硅化物上形成发射极，在发射极上的基极和在基极上的集电极来制造。

4. 发明授权

US09076730B2 Metal silicide thin film, ultra-shallow junctions, semiconductor device and method of making 有权
标题翻译：金属硅化物薄膜，超浅结，半导体器件及其制造方法
公开(公告)号：US09076730B2
公开(公告)日：2015-07-07
申请号：US13704601
申请日：2012-12-12
申请人： Dongping Wu , Peng Xu , Wei Zhang , Shi-Li Zhang
发明人： Dongping Wu , Peng Xu , Wei Zhang , Shi-Li Zhang
IPC分类号： H01L21/285 , H01L29/66 , H01L29/786 , H01L21/324
CPC分类号： H01L21/28518 , H01L21/2855 , H01L21/324 , H01L29/665 , H01L29/66575 , H01L29/66643 , H01L29/66742 , H01L29/786
摘要： A metal silicide thin film and ultra-shallow junctions and methods of making are disclosed. In the present disclosure, by using a metal and semiconductor dopant mixture as a target, a mixture film is formed on a semiconductor substrate using a physical vapor deposition (PVD) process. The mixture film is removed afterwards by wet etching, which is followed by annealing to form metal silicide thin film and ultra-shallow junctions. Because the metal and semiconductor dopant mixture is used as a target to deposit the mixture film, and the mixture film is removed by wet etching before annealing, self-limiting, ultra-thin, and uniform metal silicide film and ultra-shallow junctions are formed concurrently in semiconductor field-effect transistor fabrication processes, which are suitable for field-effect transistors at the 14 nm, 11 nm, or even further technology node.
摘要翻译：公开了一种金属硅化物薄膜和超浅结的制造方法。在本公开中，通过使用金属和半导体掺杂剂混合物作为靶，使用物理气相沉积（PVD）工艺在半导体衬底上形成混合膜。然后通过湿蚀刻除去混合物膜，随后退火以形成金属硅化物薄膜和超浅结。由于金属和半导体掺杂剂混合物用作沉积混合物膜的靶，并且在退火之前通过湿蚀刻除去混合物膜，形成自限制，超薄且均匀的金属硅化物膜和超浅结同时在半导体场效应晶体管制造工艺中，其适用于14nm，11nm甚至更进一步的技术节点处的场效应晶体管。

5. 发明申请

US20140315366A1 Semiconductor Device and Method of Making 有权
标题翻译：半导体器件及制造方法
公开(公告)号：US20140315366A1
公开(公告)日：2014-10-23
申请号：US13704615
申请日：2012-12-14
申请人： Dongping Wu , Chenyu Wen , Wei Zhang , Shi-Li Zhang
发明人： Dongping Wu , Chenyu Wen , Wei Zhang , Shi-Li Zhang
IPC分类号： H01L29/66 , H01L21/768 , H01L21/283
CPC分类号： H01L29/665 , H01L21/283 , H01L21/28518 , H01L21/28525 , H01L21/76802 , H01L21/76843 , H01L21/76855 , H01L21/76877 , H01L21/76889 , H01L23/485 , H01L23/53271 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure is related to semiconductor technologies and discloses a semiconductor device and its method of making. In the present disclosure, a transistor's source and drain are led out by concurrently formed metal-semiconductor compound contact regions at the source and drain and metal-semiconductor compounds in vias formed at positions corresponding to the source and drain. Because the metal-semiconductor compound has relatively low resistivity, the resistance of the metal-semiconductor compounds in the vias can be minimized. Also, because the material used to fill the vias and the material forming the source/drain contact regions are both metal-semiconductor compound, contact resistance between the material filling the vias and the metal-semiconductor compound source/drain contact regions can be minimized. Furthermore, because the material filling the vias is metal-semiconductor compound, the conducting material in the vias and dielectric material in the insulator layer can form good interface and have good adhesion properties, and the conducting material would not cause structural damage in the dielectric material. Thus, there is no need to form a barrier layer between the insulator layer and the material filling the vias.
摘要翻译：本公开涉及半导体技术，并公开了一种半导体器件及其制造方法。在本公开中，晶体管的源极和漏极由在源极和漏极处形成的通孔中形成的金属 - 半导体化合物接触区域和与源极和漏极相对应的通孔中的金属 - 半导体化合物引出。因为金属 - 半导体化合物具有相对低的电阻率，所以可以使过孔中金属 - 半导体化合物的电阻最小化。此外，由于用于填充通孔的材料和形成源极/漏极接触区域的材料都是金属 - 半导体化合物，所以填充通孔的材料与金属 - 半导体化合物源极/漏极接触区域之间的接触电阻可以被最小化。此外，由于填充过孔的材料是金属 - 半导体化合物，所以绝缘体层中的通孔和电介质材料中的导电材料可以形成良好的界面并且具有良好的粘合性能，并且导电材料不会在介电材料中引起结构损坏。因此，不需要在绝缘体层和填充通孔的材料之间形成阻挡层。

6. 发明申请

US20130026573A1 BODY CONTACT SOI TRANSISTOR STRUCTURE AND METHOD OF MAKING 有权
标题翻译：身体接触SOI晶体管结构及其制造方法
公开(公告)号：US20130026573A1
公开(公告)日：2013-01-31
申请号：US13583923
申请日：2011-04-19
申请人： Dongping Wu , Shili Zhang
发明人： Dongping Wu , Shili Zhang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/743 , H01L29/66772 , H01L29/78612 , H01L29/78615
摘要： The present invention puts forward a body-contact SOI transistor structure and method of making. The method comprises: forming a hard mask layer on the SOI; etching an opening exposing SOI bottom silicon; wet etching an SOI oxide layer through the opening; depositing a polysilicon layer at the opening followed by anisotropic dry etching; depositing an insulating dielectric layer at the opening followed by planarization; forming a gate stack structure by deposition and etching, and forming source/drain junctions of the transistor using ion implantation. By using the present invention, body contact for SOI field-effect transistors can be effectively formed, thereby eliminating floating-body effect in the SOI field-effect transistors, and improving heat dissipation capability of the SOI transistors and associated integrated circuits.
摘要翻译：本发明提出了一种体接触SOI晶体管结构及其制造方法。该方法包括：在SOI上形成硬掩模层; 蚀刻露出SOI底部硅的开口; 通过开口湿蚀刻SOI氧化物层; 在开口处沉积多晶硅层，然后进行各向异性干蚀刻; 在开口处沉积绝缘介电层，然后进行平坦化; 通过沉积和蚀刻形成栅极堆叠结构，以及使用离子注入形成晶体管的源极/漏极结。通过使用本发明，可以有效地形成用于SOI场效应晶体管的体接触，从而消除SOI场效应晶体管中的浮体效应，并提高SOI晶体管和相关集成电路的散热能力。

7. 发明申请

US20080283910A1 INTEGRATED CIRCUIT AND METHOD OF FORMING AN INTEGRATED CIRCUIT 审中-公开
标题翻译：集成电路和形成集成电路的方法
公开(公告)号：US20080283910A1
公开(公告)日：2008-11-20
申请号：US11748864
申请日：2007-05-15
申请人： Lars Dreeskornfeld , Dongping Wu , Jessica Hartwich , Juergen Holz , Arnd Scholz
发明人： Lars Dreeskornfeld , Dongping Wu , Jessica Hartwich , Juergen Holz , Arnd Scholz
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/823456 , H01L21/823431 , H01L27/088 , H01L27/0886 , H01L27/1211 , H01L29/66795 , H01L29/66818 , H01L29/785
摘要： An integrated circuit and method of forming an integrated circuit is disclosed. One embodiment includes a FinFET of a first type having a first gate electrode and a FinFET of a second type having a second gate electrode. The first gate electrode is formed in a gate groove that is defined in a semiconductor substrate and a bottom side of a portion of the second gate electrode is disposed above a main surface of the semiconductor substrate.
摘要翻译：公开了一种形成集成电路的集成电路和方法。一个实施例包括具有第一栅极和第二类型的具有第二栅电极的FinFET的第一类型的FinFET。第一栅电极形成在限定在半导体衬底中的栅极沟槽中，并且第二栅电极的一部分的底侧设置在半导体衬底的主表面上方。

8. 发明授权

US07202535B2 Manufacturing method for an integrated semiconductor structure and corresponding integrated semiconductor structure 有权
标题翻译：集成半导体结构的制造方法和相应的集成半导体结构
公开(公告)号：US07202535B2
公开(公告)日：2007-04-10
申请号：US11183224
申请日：2005-07-14
申请人： Matthias Goldbach , Dongping Wu
发明人： Matthias Goldbach , Dongping Wu
IPC分类号： H01L29/94
CPC分类号： H01L21/823857
摘要： The present invention provides a manufacturing method for an integrated semiconductor structure and a corresponding integrated semiconductor structure. The manufacturing method comprises the steps of: providing a semiconductor substrate (1) having an upper surface (O) and having first and second transistor regions (T1, T2); wherein said first transistor region (T1) is a n-MOSFET region and second transistor region (T2) is a p-MOSFET region; forming a gate structure on said first and second transistor region (T1, T2) including at least one gate dielectric layer (2, 3, 10c, 17, 25) and one gate layer (4; 35; 50, 60) in each of said first and second transistor regions (T1, T2); wherein said gate layer (4; 35; 60) in said second transistor region (T2) is made of negatively doped polysilicon; wherein said at least one gate dielectric layer (2, 10c, 17) in said first transistor region (T1) comprises a first dielectric layer (2, 10c, 17); wherein said at least one gate dielectric layer (2, 3, 10c, 25, 25′) in said second transistor region (T2) comprises an interfacial dielectric layer (2; 25; 25′) located adjacent to said gate layer (4; 35; 60) in said second transistor region (T2), which interfacial dielectric layer (2; 25; 25′) forms an Al2O3 containing interface on said gate layer (4; 35; 60) in said second transistor region (T2) causing a Fermi-pinning effect; and wherein said first transistor region (T1) does not include said interfacial dielectric layer (2; 25; 25′).
摘要翻译：本发明提供了一种用于集成半导体结构和相应的集成半导体结构的制造方法。该制造方法包括以下步骤：提供具有上表面（O）并具有第一和第二晶体管区域（T 1，T 2）的半导体衬底（1）; 其中所述第一晶体管区域（T 1）是n-MOSFET区域，第二晶体管区域（T 2）是p-MOSFET区域; 在包括至少一个栅极介电层（2,3,10c，17,25）和一个栅极层（4; 35; 50,60）的所述第一和第二晶体管区域（T 1，T 2）上形成栅极结构，在所述第一和第二晶体管区域（T 1，T 2）的每一个中; 其中所述第二晶体管区域（T 2）中的所述栅极层（4; 35; 60）由负掺杂多晶硅制成; 其中所述第一晶体管区域（T 1）中的所述至少一个栅介质层（2,10c，17）包括第一介电层（2,10c，17）; 其中所述第二晶体管区域（T 2）中的所述至少一个栅极电介质层（2,3，10c，25,25'）包括邻近所述栅极层的界面电介质层（2; 25; 25'） 4; 35; 60）在所述第二晶体管区域（T 2）中，所述界面电介质层（2; 25; 25'）形成含有Al 2 N 3 O 3界面在所述第二晶体管区域（T 2）中的所述栅极层（4; 35; 60）上引起费米钉扎效应; 并且其中所述第一晶体管区域（T 1）不包括所述界面电介质层（2; 25; 25'）。

9. 发明申请

US20230075464A1 Touch Operation Method and Device 有权
公开(公告)号：US20230075464A1
公开(公告)日：2023-03-09
申请号：US17920838
申请日：2021-04-21
申请人： Dongping Wu , Weigang Cai , Leilei Chen , Liui Tian , Danhong Li , Hang Li
发明人： Dongping Wu , Weigang Cai , Leilei Chen , Liui Tian , Danhong Li , Hang Li
IPC分类号： G06F3/0488 , G06F3/0346 , G06F3/04847
摘要： A touch operation method applied to an electronic device having a curved screen, where the curved screen includes a side edge of the electronic device. After detecting that the side edge is touched, the electronic device determines a target region, where the target region is a contact region of a user on the side edge in a holding mode. The electronic device prompts a location of the target region. After detecting a touch operation performed by the user on the target region, the electronic device performs a corresponding response operation for the touch operation.

10. 发明授权

US09209029B2 Asymmetrical gate MOS device and method of making 有权
标题翻译：非对称栅MOS器件及其制作方法
公开(公告)号：US09209029B2
公开(公告)日：2015-12-08
申请号：US14113705
申请日：2011-12-28
申请人： Dongping Wu , Cheng Hu , Lun Zhu , Zhiwei Zhu , Shili Zhang , Wei Zhang
发明人： Dongping Wu , Cheng Hu , Lun Zhu , Zhiwei Zhu , Shili Zhang , Wei Zhang
IPC分类号： H01L21/336 , H01L21/28 , H01L21/285 , H01L29/04 , H01L29/66 , H01L29/78 , H01L29/49 , H01L21/265
CPC分类号： H01L21/28008 , H01L21/26586 , H01L21/28097 , H01L21/28105 , H01L21/2815 , H01L21/28518 , H01L29/04 , H01L29/4975 , H01L29/66575 , H01L29/6659 , H01L29/66659 , H01L29/7835
摘要： An asymetric gate MOS device is disclosed. The gate is a metal gate, and the metal gate has a different work function on the source side from that on the drain side of the MOS device, so that the overall performance parameters of the MOS device are more optimized. A method of making an asymetric gate MOS device is also disclosed. In the method, dopant ions are implanted into the gate of the MOS device, so as to cause the gate to have a different work function on the source side from that on the drain side of the MOS device. As a result, the overall performance parameters of the MOS device are more optimized. The method can be easily implemented.
摘要翻译：公开了一种非对称门MOS器件。栅极是金属栅极，金属栅极在源极侧与MOS器件的漏极侧具有不同的功函，使得MOS器件的整体性能参数更加优化。还公开了制造不对称栅极MOS器件的方法。在该方法中，将掺杂剂离子注入到MOS器件的栅极中，以使栅极在源极侧与MOS器件的漏极侧上具有不同的功函数。结果，MOS器件的整体性能参数更加优化。该方法可以很容易地实现。

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