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1. 发明申请

US20140070363A1 ELECTRONIC ANTI-FUSE 有权
标题翻译：电子防熔丝
公开(公告)号：US20140070363A1
公开(公告)日：2014-03-13
申请号：US13608183
申请日：2012-09-10
申请人： Junjing Bao , Griselda Bonilla , Samuel S. Choi , Ronald G. Filippi , Naftali Eliahu Lustig , Andrew H. Simon
发明人： Junjing Bao , Griselda Bonilla , Samuel S. Choi , Ronald G. Filippi , Naftali Eliahu Lustig , Andrew H. Simon
IPC分类号： H01L23/525 , H01L21/768
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： An electronic anti-fuse structure, the structure including an Mx level comprising a first Mx metal and a second Mx metal, a dielectric layer located above the Mx level, an Mx+1 level located above the dielectric layer; and a metallic element in the dielectric layer and positioned between the first Mx metal and the second Mx metal, wherein the metallic element is insulated from both the first Mx metal and the second Mx metal.
摘要翻译：一种电子反熔丝结构，该结构包括包含第一Mx金属和第二Mx金属的Mx级，位于Mx级上方的电介质层，位于介电层上方的Mx + 1级; 以及金属元件，位于所述第一Mx金属和所述第二Mx金属之间，所述金属元件与所述第一Mx金属和所述第二Mx金属绝缘。

2. 发明授权

US08736020B2 Electronic anti-fuse 有权
标题翻译：电子防熔丝
公开(公告)号：US08736020B2
公开(公告)日：2014-05-27
申请号：US13608183
申请日：2012-09-10
申请人： Junjing Bao , Griselda Bonilla , Samuel S. Choi , Ronald G. Filippi , Naftali Eliahu Lustig , Andrew H. Simon
发明人： Junjing Bao , Griselda Bonilla , Samuel S. Choi , Ronald G. Filippi , Naftali Eliahu Lustig , Andrew H. Simon
IPC分类号： H01L23/52
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： An electronic anti-fuse structure, the structure including an Mx level comprising a first Mx metal and a second Mx metal, a dielectric layer located above the Mx level, an Mx+1 level located above the dielectric layer; and a metallic element in the dielectric layer and positioned between the first Mx metal and the second Mx metal, wherein the metallic element is insulated from both the first Mx metal and the second Mx metal.
摘要翻译：一种电子反熔丝结构，该结构包括包含第一Mx金属和第二Mx金属的Mx级，位于Mx级上方的电介质层，位于介电层上方的Mx + 1级; 以及金属元件，位于所述第一Mx金属和所述第二Mx金属之间，所述金属元件与所述第一Mx金属和所述第二Mx金属绝缘。

3. 发明授权

US08836124B2 Fuse and integrated conductor 有权
标题翻译：保险丝和集成导体
公开(公告)号：US08836124B2
公开(公告)日：2014-09-16
申请号：US13414742
申请日：2012-03-08
申请人： Griselda Bonilla , Kaushik Chanda , Samuel Sung Shik Choi , Ronald G. Filippi , Stephan Grunow , Naftali Eliahu Lustig , Andrew H. Simon
发明人： Griselda Bonilla , Kaushik Chanda , Samuel Sung Shik Choi , Ronald G. Filippi , Stephan Grunow , Naftali Eliahu Lustig , Andrew H. Simon
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/5256 , H01L23/53233 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A fuse structure includes within an aperture within a dielectric layer located over a substrate that exposes a conductor contact layer within the substrate a seed layer interposed between the conductor contact layer and another conductor layer. The seed layer includes a doped copper material that includes a dopant immobilized predominantly within the seed layer. The fuse structure may be severed while not severing a conductor interconnect structure also located over the substrate that exposes a second conductor contact layer within a second aperture. In contrast with the fuse structure that includes the doped seed layer having the immobilized dopant, the interconnect structure includes a doped seed layer having a mobile dopant.
摘要翻译：熔丝结构包括在位于衬底之上的电介质层内的孔内，孔暴露在衬底内的导体接触层，介于导体接触层和另一导体层之间的晶种层。种子层包括掺杂的铜材料，其包括主要在种子层内固定的掺杂剂。可以切断熔丝结构，同时不切断也位于衬底上的导体互连结构，所述导体互连结构在第二孔内暴露第二导体接触层。与包括具有固定化掺杂剂的掺杂种子层的熔丝结构相反，互连结构包括具有可移动掺杂剂的掺杂种子层。

4. 发明申请

US20130234284A1 Fuse and Integrated Conductor 有权
标题翻译：保险丝和集成导体
公开(公告)号：US20130234284A1
公开(公告)日：2013-09-12
申请号：US13414742
申请日：2012-03-08
申请人： Griselda Bonilla , Kaushik Chanda , Samuel Sung Shik Choi , Ronald G. Filippi , Stephan Grunow , Naftali Eliahu Lustig , Andrew H. Simon
发明人： Griselda Bonilla , Kaushik Chanda , Samuel Sung Shik Choi , Ronald G. Filippi , Stephan Grunow , Naftali Eliahu Lustig , Andrew H. Simon
IPC分类号： H01L23/525 , H01L21/02
CPC分类号： H01L23/5256 , H01L23/53233 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A fuse structure includes within an aperture within a dielectric layer located over a substrate that exposes a conductor contact layer within the substrate a seed layer interposed between the conductor contact layer and another conductor layer. The seed layer includes a doped copper material that includes a dopant immobilized predominantly within the seed layer. The fuse structure may be severed while not severing a conductor interconnect structure also located over the substrate that exposes a second conductor contact layer within a second aperture. In contrast with the fuse structure that includes the doped seed layer having the immobilized dopant, the interconnect structure includes a doped seed layer having a mobile dopant.
摘要翻译：熔丝结构包括在位于衬底之上的电介质层内的孔内，孔暴露在衬底内的导体接触层，介于导体接触层和另一导体层之间的晶种层。种子层包括掺杂的铜材料，其包括主要在种子层内固定的掺杂剂。可以切断熔丝结构，同时不切断也位于衬底上的导体互连结构，所述导体互连结构在第二孔内暴露第二导体接触层。与包括具有固定化掺杂剂的掺杂种子层的熔丝结构相反，互连结构包括具有可移动掺杂剂的掺杂种子层。

5. 发明申请

US20090093114A1 METHOD OF FORMING A DUAL-DAMASCENE STRUCTURE USING AN UNDERLAYER 审中-公开
标题翻译：使用底层形成双重结构结构的方法
公开(公告)号：US20090093114A1
公开(公告)日：2009-04-09
申请号：US11869043
申请日：2007-10-09
申请人： Sean David Burns , Matthew Earl Colburn , Naftali Eliahu Lustig , David R. Medeiros , Kaushal Patel , Libor Vyklicky
发明人： Sean David Burns , Matthew Earl Colburn , Naftali Eliahu Lustig , David R. Medeiros , Kaushal Patel , Libor Vyklicky
IPC分类号： H01L21/4763
CPC分类号： H01L21/022 , H01L21/31144 , H01L21/312 , H01L21/76808
摘要： A method of forming a dual-damascene wire. The method includes forming a via opening in a dielectric layer, filling the via opening with a polymeric formation including at least about 6% by weight of solids of thermal acid generator; heating the polymeric underlayer to a temperature greater than room temperature but less than about 180° C.; lithographically forming a trench in the dielectric layer and filling the via opening and the trench with an electrical conductor, a top surface of the electrical conductor substantially co-planer with the top surface of the second dielectric capping layer.
摘要翻译：一种形成双镶嵌线的方法。该方法包括在电介质层中形成通孔，通过包含至少约6重量％的热酸发生器固体的聚合物填充通孔开口; 将聚合物底层加热到大于室温但小于约180℃的温度; 在电介质层中光刻地形成沟槽并用电导体填充通孔开口和沟槽，电导体的顶表面与第二电介质覆盖层的顶表面基本共面。

6. 发明申请

US20080026568A1 INTERCONNECT STRUCTURE AND PROCESS OF MAKING THE SAME 有权
标题翻译：互连结构及其制作方法
公开(公告)号：US20080026568A1
公开(公告)日：2008-01-31
申请号：US11461137
申请日：2006-07-31
申请人： Theodorus Eduardus Standaert , Pegeen M. Davis , John Anthony Fitzsimmons , Stephen Edward Greco , Tze-Man Ko , Naftali Eliahu Lustig , Lee Matthew Nicholson , Sujatha Sankaran
发明人： Theodorus Eduardus Standaert , Pegeen M. Davis , John Anthony Fitzsimmons , Stephen Edward Greco , Tze-Man Ko , Naftali Eliahu Lustig , Lee Matthew Nicholson , Sujatha Sankaran
IPC分类号： H01L21/4763
CPC分类号： H01L21/76808 , H01L21/76805 , H01L21/76814 , H01L21/76846 , H01L2924/0002 , H01L2924/00
摘要： A method of forming an interconnect structure in an inter-layer dielectric (ILD) material, the method include the steps of creating one or more via openings in the ILD material; forming a first liner covering at least one of the one or more via openings; creating one or more trench openings on top of at least one of the one or more via openings covered by the first liner; and forming a second liner covering the trenching openings and at least part of the first liner. An interconnect structure formed by the method is also provided.
摘要翻译：一种在层间电介质（ILD）材料中形成互连结构的方法，所述方法包括以下步骤：在ILD材料中形成一个或多个通路孔; 形成覆盖所述一个或多个通孔开口中的至少一个的第一衬垫; 在由所述第一衬垫覆盖的所述一个或多个通孔中的至少一个的顶部上形成一个或多个沟槽开口; 以及形成覆盖所述下料开口和所述第一衬里的至少一部分的第二衬里。还提供了通过该方法形成的互连结构。

7. 发明授权

US06573606B2 Chip to wiring interface with single metal alloy layer applied to surface of copper interconnect 有权
标题翻译：芯片到布线接口，单个金属合金层应用于铜互连表面
公开(公告)号：US06573606B2
公开(公告)日：2003-06-03
申请号：US09881444
申请日：2001-06-14
申请人： Carlos Juan Sambucetti , Xiaomeng Chen , Soon-Cheon Seo , Birenda Nath Agarwala , Chao-Kun Hu , Naftali Eliahu Lustig , Stephen Edward Greco
发明人： Carlos Juan Sambucetti , Xiaomeng Chen , Soon-Cheon Seo , Birenda Nath Agarwala , Chao-Kun Hu , Naftali Eliahu Lustig , Stephen Edward Greco
IPC分类号： H01L2144
CPC分类号： H01L23/53238 , H01L21/76849 , H01L2924/0002 , H01L2924/00
摘要： In the invention an electrically isolated copper interconnect structural interface is provided involving a single, about 50-300 A thick, alloy capping layer, that controls diffusion and electromigration of the interconnection components and reduces the overall effective dielectric constant of the interconnect; the capping layer being surrounded by a material referred to in the art as hard mask material that can provide a resist for subsequent reactive ion etching operations, and there is also provided the interdependent process steps involving electroless deposition in the fabrication of the structural interface. The single layer alloy metal barrier in the invention is an alloy of the general type A—X—Y, where A is a metal taken from the group of cobalt (Co) and nickel (Ni), X is a member taken from the group of tungsten (W), tin (Sn), and silicon (Si), and Y is a member taken from the group of phosphorous (P) and boron (B); having a thickness in the range of 50 to 300 Angstroms.
摘要翻译：在本发明中，提供了电隔离的铜互连结构界面，其涉及单个约50-300A厚的合金覆盖层，其控制互连部件的扩散和电迁移并且降低互连的整体有效介电常数; 封盖层被本领域中称为材料所包围的材料包围，其可以为随后的反应离子蚀刻操作提供抗蚀剂，并且还提供了在结构界面的制造中涉及无电沉积的相互依赖的工艺步骤。本发明中的单层合金金属阻挡层是一般型AXY的合金，其中A是从钴（Co）和镍（Ni）中取出的金属，X是取自钨（W ），锡（Sn）和硅（Si），Y是从磷（P）和硼（B）取代的成员; 厚度在50至300埃的范围内。

8. 发明授权

US6020264A Method and apparatus for in-line oxide thickness determination in chemical-mechanical polishing 失效
标题翻译：化学机械抛光中在线氧化物厚度测定的方法和装置
公开(公告)号：US6020264A
公开(公告)日：2000-02-01
申请号：US792082
申请日：1997-01-31
申请人： Naftali Eliahu Lustig , William L. Guthrie , Thomas E. Sandwick
发明人： Naftali Eliahu Lustig , William L. Guthrie , Thomas E. Sandwick
IPC分类号： G01B7/06 , B24B37/013 , B24B49/04 , G01N27/22 , H01L21/304 , H01L21/3105 , H01L21/66 , C23F1/00
CPC分类号： G01B7/085 , B24B37/013 , B24B49/04 , H01L21/31053 , H01L22/20 , H01L22/12
摘要： In-line thickness measurement of a dielectric film layer on a surface of a workpiece subsequent to a polishing on a chemical-mechanical polishing machine in a polishing slurry is disclosed. The workpiece includes a given level of back-end-of-line (BEOL) structure including junctions. The measurement apparatus includes a platen and an electrode embedded within the platen. A positioning mechanism positions the workpiece above the electrode with the dielectric layer facing in a direction of the electrode. A slurry dam is used for maintaining a prescribed level of a conductive polishing slurry above the electrode, the prescribed level to ensure a desired slurry coverage of the workpiece. A capacitance sensor senses a system capacitance C in accordance with an RC equivalent circuit model, wherein the RC equivalent circuit includes a resistance R representative of the slurry and workpiece resistances and the system capacitance C representative of the dielectric material and junction capacitances. Lastly, a capacitance-to-thickness converter converts the sensed capacitance to a dielectric thickness in accordance with a prescribed system capacitance/optical thickness calibration, wherein the prescribed calibration corresponds to the given level of BEOL structure of the workpiece.
摘要翻译：公开了在抛光浆料中的化学机械抛光机上的抛光后的工件表面上的电介质膜层的在线厚度测量。工件包括给定水平的包括路口的后端行（BEOL）结构。测量装置包括压板和嵌入在压板内的电极。定位机构将工件定位在电极上方，电介质层面向电极的方向。浆料坝用于在电极上方保持规定水平的导电抛光浆料，其规定水平以确保工件的期望的浆料覆盖。电容传感器根据RC等效电路模型感测系统电容C，其中RC等效电路包括代表浆料和工件电阻的电阻R和代表电介质材料和结电容的系统电容C。最后，电容 - 厚度转换器根据规定的系统电容/光学厚度校准将感测到的电容转换成电介质厚度，其中规定的校准对应于工件的给定水平的BEOL结构。

9. 发明授权

US08030707B2 Semiconductor structure 失效
标题翻译：半导体结构
公开(公告)号：US08030707B2
公开(公告)日：2011-10-04
申请号：US12390741
申请日：2009-02-23
申请人： Kangguo Cheng , Naftali Eliahu Lustig , Daewon Yang
发明人： Kangguo Cheng , Naftali Eliahu Lustig , Daewon Yang
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H01L21/84 , H01L27/10829 , H01L27/1087 , H01L27/1203
摘要： A method of forming a silicon-on-insulator (SOI) semiconductor structure in a substrate having a bulk semiconductor layer, a buried oxide (BOX) layer and an SOI layer. During the formation of a trench in the structure, the BOX layer is undercut. The method includes forming a dielectric material on the upper wall of the trench adjacent to the undercutting of the BOX layer and then etching the dielectric material to form a spacer. The spacer fixes the BOX layer undercut and protects it during subsequent steps of forming a bottle-shaped portion of the trench, forming a buried plate in the deep trench; and then forming a trench capacitor. There is also a semiconductor structure, preferably an SOI eDRAM structure, having a spacer which fixes the undercutting in the BOX layer.
摘要翻译：一种在具有体半导体层，掩埋氧化物（BOX）层和SOI层的衬底中形成绝缘体上硅（SOI）半导体结构的方法。在结构中形成沟槽时，BOX层被切削。该方法包括在邻近BOX层的底切的沟槽的上壁上形成介电材料，然后蚀刻电介质材料以形成间隔物。间隔件固定BOX层底切并在形成沟槽的瓶形部分的后续步骤期间保护它，在深沟槽中形成掩埋板; 然后形成沟槽电容器。还存在半导体结构，优选为SOI eDRAM结构，其具有将底切固定在BOX层中的间隔物。

10. 发明申请

US20100213522A1 METHOD FOR FORMING A SEMICONDUCTOR STRUCTURE TO REMEDY BOX UNDERCUT AND STRUCTURE FORMED THEREBY 失效
标题翻译：用于形成半导体结构以获得补偿盒和其结构的方法
公开(公告)号：US20100213522A1
公开(公告)日：2010-08-26
申请号：US12390741
申请日：2009-02-23
申请人： Kangguo Cheng , Naftali Eliahu Lustig , Daewon Yang
发明人： Kangguo Cheng , Naftali Eliahu Lustig , Daewon Yang
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L21/84 , H01L27/10829 , H01L27/1087 , H01L27/1203
摘要： A method of forming a silicon-on-insulator (SOI) semiconductor structure in a substrate having a bulk semiconductor layer, a buried oxide (BOX) layer and an SOI layer. During the formation of a trench in the structure, the BOX layer is undercut. The method includes forming a dielectric material on the upper wall of the trench adjacent to the undercutting of the BOX layer and then etching the dielectric material to form a spacer. The spacer fixes the BOX layer undercut and protects it during subsequent steps of forming a bottle-shaped portion of the trench, forming a buried plate in the deep trench; and then forming a trench capacitor. There is also a semiconductor structure, preferably an SOI eDRAM structure, having a spacer which fixes the undercutting in the BOX layer.
摘要翻译：一种在具有体半导体层，掩埋氧化物（BOX）层和SOI层的衬底中形成绝缘体上硅（SOI）半导体结构的方法。在结构中形成沟槽时，BOX层被切削。该方法包括在邻近BOX层的底切的沟槽的上壁上形成介电材料，然后蚀刻电介质材料以形成间隔物。间隔件固定BOX层底切并在形成沟槽的瓶形部分的后续步骤期间保护它，在深沟槽中形成掩埋板; 然后形成沟槽电容器。还存在半导体结构，优选为SOI eDRAM结构，其具有将BOX层中的底切固定的间隔物。

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