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1. 发明授权

US08381283B2 Information processing apparatus and method of controlling program execution of same 有权
公开(公告)号：US08381283B2
公开(公告)日：2013-02-19
申请号：US12292209
申请日：2008-11-13
申请人： Junichi Sato , Hitoshi Suzuki
发明人： Junichi Sato , Hitoshi Suzuki
IPC分类号： G06F12/14
CPC分类号： G06F12/1441
摘要： A CPU contained in an information processing apparatus in accordance an exemplary embodiment of the present invention outputs an access request including first access destination address information by a first program, and outputs a check request including second access destination address information when the execution program is switched from the first program to a second program as a result of a program call from the first program to the second program. A protection setting check portion contained in the information processing apparatus checks whether or not the check request including the second access destination address information conforms to protection setting for the first program based on memory protection information that is established in a memory protection information storage portion to detect a violation by a memory access request by the first program.

2. 发明授权

US08209565B2 Data processing device and bus access control method therein 有权
标题翻译：数据处理装置及总线访问控制方法
公开(公告)号：US08209565B2
公开(公告)日：2012-06-26
申请号：US12314493
申请日：2008-12-11
申请人： Yukihiko Akaike , Hitoshi Suzuki , Junichi Sato
发明人： Yukihiko Akaike , Hitoshi Suzuki , Junichi Sato
IPC分类号： G06F11/00
CPC分类号： G06F11/0772 , G06F11/0745 , G06F11/0793
摘要： A data processing device includes a computing circuit that accesses a peripheral device connected to through a internal bus, an internal bus connection circuit that is provided between the computing circuit and the internal bus, and switches an enable and a disable state of an access from the computing circuit to the internal bus, an exception notification controller that outputs an exception occurrence notification signal to the computing circuit based on an error occurred in the peripheral device, and a bus disablement controller that instructs the internal bus connection circuit to disable an access from the computing circuit to the internal bus in accordance with the notification of the exception occurrence notification signal, and instructs the internal bus connection circuit to cancel the disablement of the access in accordance with a start of an exception processing based on the exception occurrence notification signal.
摘要翻译：数据处理装置包括：计算电路，其访问通过内部总线连接的外围设备;内部总线连接电路，其设置在所述计算电路和所述内部总线之间，并且从所述内部总线切换访问的使能和禁用状态计算电路到内部总线，异常通知控制器，其基于外围设备中发生的错误向计算电路输出异常发生通知信号;以及总线禁用控制器，其指示内部总线连接电路禁止从根据异常发生通知信号的通知计算电路到内部总线，并且根据异常发生通知信号的异常处理的开始，指示内部总线连接电路取消对该访问的禁止。

3. 发明申请

US20090138963A1 Information processing apparatus and method of controlling program execution of same 有权
标题翻译：控制程序执行的信息处理装置及方法
公开(公告)号：US20090138963A1
公开(公告)日：2009-05-28
申请号：US12292209
申请日：2008-11-13
申请人： Junichi Sato , Hitoshi Suzuki
发明人： Junichi Sato , Hitoshi Suzuki
IPC分类号： H04L9/32
CPC分类号： G06F12/1441
摘要： A CPU contained in an information processing apparatus in accordance an exemplary embodiment of the present invention outputs an access request including first access destination address information by a first program, and outputs a check request including second access destination address information when the execution program is switched from the first program to a second program as a result of a program call from the first program to the second program. A protection setting check portion contained in the information processing apparatus checks whether or not the check request including the second access destination address information conforms to protection setting for the first program based on memory protection information that is established in a memory protection information storage portion to detect a violation by a memory access request by the first program.
摘要翻译：包含在根据本发明的示例性实施例的信息处理设备中的CPU通过第一程序输出包括第一访问目的地地址信息的访问请求，并且当执行程序被切换时输出包括第二访问目的地地址信息的检查请求作为从第一程序到第二程序的程序调用的结果的第二程序的第一程序。包含在信息处理设备中的保护设置检查部分基于在存储器保护信息存储部分中建立的存储器保护信息来检查包括第二接入目的地地址信息的检查请求是否符合第一程序的保护设置，以检测由第一个程序的内存访问请求的违规。

4. 发明申请

US20090172332A1 Information processing apparatus and method of updating stack pointer 失效
标题翻译：更新堆栈指针的信息处理装置和方法
公开(公告)号：US20090172332A1
公开(公告)日：2009-07-02
申请号：US12314073
申请日：2008-12-03
申请人： Rika Ono , Hitoshi Suzuki , Junichi Sato
发明人： Rika Ono , Hitoshi Suzuki , Junichi Sato
IPC分类号： G06F12/14
CPC分类号： G06F12/1425
摘要： A instruction execution part of an information processing device outputs an access request including a first address information to specify an access destination based on an execution of an access command of an address space in a memory. The instruction execution part also outputs a check request including a second address information to specify a stack pointer point after extension based on an execution of a stack extension command to extend a stack included in the address space in the memory by updating a stack pointer. A protection violation detection section of the information processing device detects whether the access destination includes the plurality of the partial spaces by collating the first information with the memory protection information stored in the memory protection information storage section.
摘要翻译：信息处理装置的指令执行部分基于存储器中的地址空间的访问命令的执行来输出包括第一地址信息的访问请求以指定访问目的地。指令执行部分还输出包括第二地址信息的检查请求，以便在扩展之后基于堆栈扩展命令的执行来指定堆栈指针点，以通过更新堆栈指针来扩展包含在存储器中的地址空间中的栈。信息处理设备的保护违规检测部分通过将第一信息与存储在存储器保护信息存储部分中的存储器保护信息进行对照来检测接入目的地是否包括多个部分空间。

5. 发明授权

US08234476B2 Information processing apparatus and method of updating stack pointer 失效
标题翻译：更新堆栈指针的信息处理装置和方法
公开(公告)号：US08234476B2
公开(公告)日：2012-07-31
申请号：US12314073
申请日：2008-12-03
申请人： Rika Ono , Hitoshi Suzuki , Junichi Sato
发明人： Rika Ono , Hitoshi Suzuki , Junichi Sato
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F15/00 , G06F9/30 , G06F9/40
CPC分类号： G06F12/1425
摘要： A instruction execution part of an information processing device outputs an access request including a first address information to specify an access destination based on an execution of an access command of an address space in a memory. The instruction execution part also outputs a check request including a second address information to specify a stack pointer point after extension based on an execution of a stack extension command to extend a stack included in the address space in the memory by updating a stack pointer. A protection violation detection section of the information processing device detects whether the access destination includes the plurality of the partial spaces by collating the first information with the memory protection information stored in the memory protection information storage section.
摘要翻译：信息处理装置的指令执行部分基于存储器中的地址空间的访问命令的执行来输出包括第一地址信息的访问请求以指定访问目的地。指令执行部分还输出包括第二地址信息的检查请求，以便在扩展之后基于堆栈扩展命令的执行来指定堆栈指针点，以通过更新堆栈指针来扩展包含在存储器中的地址空间中的栈。信息处理设备的保护违规检测部分通过将第一信息与存储在存储器保护信息存储部分中的存储器保护信息进行对照来检测接入目的地是否包括多个部分空间。

6. 发明授权

US08209448B2 Data processing apparatus and method of protecting a peripheral device in data processing apparatus 有权
标题翻译：数据处理装置和数据处理装置中的外围设备的保护方法
公开(公告)号：US08209448B2
公开(公告)日：2012-06-26
申请号：US12292256
申请日：2008-11-14
申请人： Junichi Sato , Hitoshi Suzuki
发明人： Junichi Sato , Hitoshi Suzuki
IPC分类号： G06F3/00 , G06F13/00 , G06F12/00
CPC分类号： G06F21/82 , G06F21/78 , G06F2221/2113
摘要： A data processing apparatus includes an arithmetic circuit and a peripheral device protection circuit that controls access of the arithmetic circuit to the peripheral devices. The peripheral device protection circuit has a first protection preset value and a second protection preset value set as a protection level higher than that of the first protection preset value. The peripheral device protection circuit includes: a setting selection circuit that generates access permission/denial information by referring to the first protection preset value and the second protection preset value when the arithmetic circuit operates at a first operation authority level, or by referring to the second protection preset value when the arithmetic circuit operates at the second operation authority level. An access protection circuit that determines permission/denial of access to the peripheral devices based on access information output from the arithmetic circuit and the access permission/denial information.
摘要翻译：数据处理装置包括运算电路和外围设备保护电路，其控制运算电路对周边设备的访问。外围设备保护电路具有设置为高于第一保护预设值的保护级别的第一保护预设值和第二保护预置值。外围设备保护电路包括：设置选择电路，当运算电路以第一操作授权级别运行时，通过参考第一保护预置值和第二保护预设值产生访问允许/拒绝信息，或者参考第二运算电路在第二操作权限级别运行时的保护预置值。访问保护电路，根据从算术电路输出的访问信息和访问许可/拒绝信息，确定对外围设备的访问权限/拒绝。

7. 发明申请

US20090172231A1 Data processing device and bus access control method therein 有权
标题翻译：数据处理装置及总线访问控制方法
公开(公告)号：US20090172231A1
公开(公告)日：2009-07-02
申请号：US12314493
申请日：2008-12-11
申请人： Yukihiko Akaike , Hitoshi Suzuki , Junichi Sato
发明人： Yukihiko Akaike , Hitoshi Suzuki , Junichi Sato
IPC分类号： G06F13/24
CPC分类号： G06F11/0772 , G06F11/0745 , G06F11/0793
摘要： A data processing device includes a computing circuit that accesses a peripheral device connected to through a internal bus, an internal bus connection circuit that is provided between the computing circuit and the internal bus, and switches an enable and a disable state of an access from the computing circuit to the internal bus, an exception notification controller that outputs an exception occurrence notification signal to the computing circuit based on an error occurred in the peripheral device, and a bus disablement controller that instructs the internal bus connection circuit to disable an access from the computing circuit to the internal bus in accordance with the notification of the exception occurrence notification signal, and instructs the internal bus connection circuit to cancel the disablement of the access in accordance with a start of an exception processing based on the exception occurrence notification signal.
摘要翻译：数据处理装置包括：计算电路，其访问通过内部总线连接的外围设备;内部总线连接电路，其设置在所述计算电路和所述内部总线之间，并且从所述内部总线切换访问的使能和禁用状态计算电路到内部总线，异常通知控制器，其基于外围设备中发生的错误向计算电路输出异常发生通知信号;以及总线禁用控制器，其指示内部总线连接电路禁止从根据异常发生通知信号的通知计算电路到内部总线，并且根据异常发生通知信号的异常处理的开始，指示内部总线连接电路取消对该访问的禁止。

8. 发明申请

US20090144465A1 Data processing apparatus and method of protecting a peripheral device in data processing apparatus 有权
标题翻译：数据处理装置和数据处理装置中的外围设备的保护方法
公开(公告)号：US20090144465A1
公开(公告)日：2009-06-04
申请号：US12292256
申请日：2008-11-14
申请人： Junichi Sato , Hitoshi Suzuki
发明人： Junichi Sato , Hitoshi Suzuki
IPC分类号： G06F21/04
CPC分类号： G06F21/82 , G06F21/78 , G06F2221/2113
摘要： A data processing apparatus includes an arithmetic circuit and a peripheral device protection circuit that controls access of the arithmetic circuit to the peripheral devices. The peripheral device protection circuit has a first protection preset value and a second protection preset value set as a protection level higher than that of the first protection preset value. The peripheral device protection circuit includes: a setting selection circuit that generates access permission/denial information by referring to the first protection preset value and the second protection preset value when the arithmetic circuit operates at a first operation authority level, or by referring to the second protection preset value when the arithmetic circuit operates at the second operation authority level. An access protection circuit that determines permission/denial of access to the peripheral devices based on access information output from the arithmetic circuit and the access permission/denial information.
摘要翻译：数据处理装置包括运算电路和外围设备保护电路，其控制运算电路对周边设备的访问。外围设备保护电路具有设置为高于第一保护预设值的保护级别的第一保护预设值和第二保护预置值。外围设备保护电路包括：设置选择电路，当运算电路以第一操作授权级别运行时，通过参考第一保护预置值和第二保护预设值产生访问允许/拒绝信息，或者参考第二运算电路在第二操作权限级别运行时的保护预置值。访问保护电路，根据从算术电路输出的访问信息和访问许可/拒绝信息，确定对外围设备的访问权限/拒绝。

9. 发明授权

US08873184B2 Tape drive device, tape library device, and data storing method 有权
标题翻译：磁带驱动装置，磁带库装置和数据存储方法
公开(公告)号：US08873184B2
公开(公告)日：2014-10-28
申请号：US13528892
申请日：2012-06-21
申请人： Junichi Sato
发明人： Junichi Sato
IPC分类号： G11B5/008 , G11B20/10 , G11B15/02 , G11B23/04 , G11B15/68
CPC分类号： G11B20/10 , G11B15/02 , G11B15/689 , G11B23/042 , G11B2020/10981 , G11B2220/45 , G11B2220/60 , G11B2220/90
摘要： A tape drive device for storing data in a tape cartridge includes a comparison unit that compares a transfer speed of the data transmitted from a host machine to the tape drive device with a speed threshold, a speed determination unit that determines a writing speed to a tape cartridge using the speed threshold, and a data write unit that writes data to the tape cartridge, the data write unit writing data to the magnetic tape provided for the tape cartridge when the determined writing speed is higher than the speed threshold, and the data write unit writing subsequent data following data written to the magnetic tape to the non-volatile semiconductor memory provided for the tape cartridge when the determined writing speed is lower than the speed threshold.
摘要翻译：一种用于将数据存储在磁带盒中的磁带驱动装置，包括：比较单元，其将从主机发送的数据的传送速度与带驱动装置的速度阈值进行比较;速度确定单元，确定对磁带的写入速度并且当所确定的写入速度高于速度阈值时，数据写入单元向数据写入单元写入数据到数据写入单元，该数据写入单元向磁带盒提供的磁带写入数据，并且数据写入当确定的写入速度低于速度阈值时，将写入磁带的数据的后续数据写入到提供给带盒的非易失性半导体存储器。

10. 发明授权

US08484697B2 Content distribution system, content distribution method and program 有权
标题翻译：内容分发系统，内容分发方式和程序
公开(公告)号：US08484697B2
公开(公告)日：2013-07-09
申请号：US12523854
申请日：2007-12-26
申请人： Junichi Sato , Akira Kobayashi , Katsuhiro Ochiai , Motonobu Kimura , Kaname Naito , Shuhei Miura
发明人： Junichi Sato , Akira Kobayashi , Katsuhiro Ochiai , Motonobu Kimura , Kaname Naito , Shuhei Miura
IPC分类号： G06F7/04 , G06F17/30 , G06F15/173
CPC分类号： H04L63/168 , G06F21/10 , G06F21/33 , H04L63/0838
摘要： A content distribution system. A distribution management and unauthorized operation management device generates a one-time URL by using URL of content information specified by a user terminal and transmits the one-time URL and bandwidth information concerning the content information to the user terminal. A session control server extracts the one-time URL from a session control message transmitted from the user terminal, transmits it to the distribution management and unauthorized operation management device, and establishes a session between the content distribution server and the user terminal according to an authentication result performed by using the one-time URL transmitted from the distribution management and unauthorized operation management device and a correlation result obtained by correlating the bandwidth information contained in the session control message transmitted from the user terminal with the bandwidth information transmitted together with the authentication result from the distribution management and unauthorized operation management device.
摘要翻译：内容分发系统。分发管理和未经授权的操作管理设备通过使用由用户终端指定的内容信息的URL来生成一次性URL，并将一次性URL和关于内容信息的带宽信息发送给用户终端。会话控制服务器从用户终端发送的会话控制消息中提取一次性URL，将其发送到分发管理和未经授权的操作管理设备，并根据认证建立内容分发服务器与用户终端之间的会话通过使用从分发管理和未经授权的操作管理装置发送的一次性URL执行的结果以及将从用户终端发送的会话控制消息中包含的带宽信息与认证结果一起发送的带宽信息相关联的相关结果从配送管理和未经授权的运营管理设备。

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