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1. 发明授权

US06532528B1 Data processor and data processor system having multiple modes of address indexing and operation 有权
标题翻译：数据处理器和数据处理器系统具有多种地址索引和操作模式
公开(公告)号：US06532528B1
公开(公告)日：2003-03-11
申请号：US09563753
申请日：2000-05-01
申请人： Junichi Nishimoto , Osamu Nishii , Fumio Arakawa , Susumu Narita , Masayuki Ito , Makoto Toda , Kunio Uchiyama
发明人： Junichi Nishimoto , Osamu Nishii , Fumio Arakawa , Susumu Narita , Masayuki Ito , Makoto Toda , Kunio Uchiyama
IPC分类号： G06F1210
CPC分类号： G06F12/1027 , G06F2212/652
摘要： A data processor in which a speed of an address translating operation is raised is disclosed. A translation lookaside buffer is divided into a buffer for data and a buffer for instruction, address translation information for instruction is also stored into a translation lookaside buffer for data, and when a translation miss occurs in a translation lookaside buffer for instruction, new address translation information is fetched from the translation lookaside buffer for data. A high speed of the address translating operation can be realized as compared with that in case of obtaining address translation information from an external address translation table each time a translation miss occurs in the translation lookaside buffer for instruction.
摘要翻译：公开了一种提高地址转换操作速度的数据处理器。翻译后备缓冲区被分为用于数据的缓冲器和用于指令的缓冲器，用于指令的地址转换信息也被存储到用于数据的翻译后备缓冲器中，并且当用于指令的翻译后备缓冲器中发生翻译错误时，新的地址转换从数据的翻译后备缓冲区中提取信息。与每次在用于指令的翻译后备缓冲器中发生翻译缺口时从外部地址转换表获得地址转换信息的情况相比，可以实现地址转换操作的高速度。

2. 发明授权

US6092172A Data processor and data processing system having two translation lookaside buffers 失效
标题翻译：具有两个翻译后备缓冲器的数据处理器和数据处理系统
公开(公告)号：US6092172A
公开(公告)日：2000-07-18
申请号：US950668
申请日：1997-10-15
申请人： Junichi Nishimoto , Osamu Nishii , Fumio Arakawa , Susumu Narita , Masayuki Ito , Makoto Toda , Kunio Uchiyama
发明人： Junichi Nishimoto , Osamu Nishii , Fumio Arakawa , Susumu Narita , Masayuki Ito , Makoto Toda , Kunio Uchiyama
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/1027 , G06F2212/652
摘要： A data processor in which a speed of an address translating operation is raised is disclosed. A translation lookaside buffer is divided into a buffer for data and a buffer for instruction, address translation information for instruction is also stored into a translation lookaside buffer for data, and when a translation miss occurs in a translation lookaside buffer for instruction, new address translation information is fetched from the translation lookaside buffer for data. A high speed of the address translating operation can be realized as compared with that in case of obtaining address translation information from an external address translation table each time a translation miss occurs in the translation lookaside buffer for instruction.
摘要翻译：公开了一种提高地址转换操作速度的数据处理器。翻译后备缓冲区被分为用于数据的缓冲器和用于指令的缓冲器，用于指令的地址转换信息也被存储到用于数据的翻译后备缓冲器中，并且当用于指令的翻译后备缓冲器中发生翻译错误时，新的地址转换从数据的翻译后备缓冲区中提取信息。与每次在用于指令的翻译后备缓冲器中发生翻译缺口时从外部地址转换表获得地址转换信息的情况相比，可以实现地址转换操作的高速度。

3. 发明授权

US06851036B1 Method and apparatus for controlling external devices through address translation buffer 失效
标题翻译：用于通过地址转换缓冲器控制外部设备的方法和装置
公开(公告)号：US06851036B1
公开(公告)日：2005-02-01
申请号：US09530787
申请日：1998-11-06
申请人： Makoto Toda , Junichi Nishimoto , Masayuki Ito , Yutaka Yoshida , Jun Hasegawa
发明人： Makoto Toda , Junichi Nishimoto , Masayuki Ito , Yutaka Yoshida , Jun Hasegawa
IPC分类号： G06F12/10 , G06F12/00
CPC分类号： G06F12/1027 , G06F12/1081
摘要： A data processing system and a data processor in which the control information for controlling an external device, especially, a device having a PCMCIA interface is stored in an address translation circuit for translating a first address outputted from a CPU to a second address in association with the first or second address.
摘要翻译：一种数据处理系统和数据处理器，其中用于控制外部设备的控制信息，特别是具有PCMCIA接口的设备被存储在地址转换电路中，用于将从CPU输出的第一地址转换为与第二地址相关联的第二地址第一或第二个地址。

4. 发明申请

US20070239960A1 Data processor and IP module for data processor 审中-公开
公开(公告)号：US20070239960A1
公开(公告)日：2007-10-11
申请号：US11809624
申请日：2007-06-02
申请人： Masayuki Ito , Fumio Arakawa , Mark Hill
发明人： Masayuki Ito , Fumio Arakawa , Mark Hill
IPC分类号： G06F12/02
CPC分类号： G06F12/1027 , G06F2212/652 , G06F2212/681
摘要： In performing address translation from a virtual address space to a physical address space, when the virtual address space is divided into an area (P0), which is subjected to the address translation by TLB, and areas (P1 and P2), which are fixedly mapped to the physical address without being subjected the address translation, future extension of the physical address become difficult. A data processor comprises an address translation unit ATU that receives virtual address output from the CPU and outputs a physical address; the ATU includes a first translation lookaside buffer UTLB, a second translation lookaside buffer DTLB, a control circuit TLB_CTL that selects one of a first and a second translation lookaside buffers and performs address translation in accordance with an area of an address space in the virtual address. Since it is adapted so that the areas (P1 and P2), which are conventionally mapped fixedly by hardware, are subjected to the address translation by the DTLB, it is possible to extend a size of the physical address space later without changing the hardware.

5. 发明授权

US07243208B2 Data processor and IP module for data processor 有权
标题翻译：用于数据处理器的数据处理器和IP模块
公开(公告)号：US07243208B2
公开(公告)日：2007-07-10
申请号：US10640855
申请日：2003-08-13
申请人： Masayuki Ito , Fumio Arakawa , Mark Hill
发明人： Masayuki Ito , Fumio Arakawa , Mark Hill
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F2212/652 , G06F2212/681
摘要： In performing address translation from a virtual address space to a physical address space, when the virtual address space is divided into an area (P0), which is subjected to the address translation by TLB, and areas (P1 and P2), which are fixedly mapped to the physical address without being subjected the address translation, future extension of the physical address become difficult. A data processor comprises an address translation unit ATU that receives virtual address output from the CPU and outputs a physical address; the ATU includes a first translation lookaside buffer UTLB, a second translation lookaside buffer DTLB, a control circuit TLB_CTL that selects one of a first and a second translation lookaside buffers and performs address translation in accordance with an area of an address space in the virtual address. Since it is adapted so that the areas (P1 and P2), which are conventionally mapped fixedly by hardware, are subjected to the address translation by the DTLB, it is possible to extend a size of the physical address space later without changing the hardware.
摘要翻译：在执行从虚拟地址空间到物理地址空间的地址转换时，当虚拟地址空间被划分成由TLB进行地址转换的区域（P 0）和区域（P 1和P 2）时，它们被固定地映射到物理地址而不受地址转换，物理地址的将来的扩展变得困难。数据处理器包括地址转换单元ATU，其接收从CPU输出的虚拟地址并输出物理地址; ATU包括第一翻译后备缓冲器UTLB，第二翻译后备缓冲器DTLB，控制电路TLB_CTL，其选择第一和第二翻译后备缓冲器中的一个并根据虚拟地址中的地址空间的区域执行地址转换。由于适配使得由硬件固定地映射的区域（P 1和P 2）由DTLB进行地址转换，所以可以稍后扩展物理地址空间的大小而不改变硬件。

6. 发明申请

US20050038973A1 Data processor and IP module for data processor 有权
标题翻译：用于数据处理器的数据处理器和IP模块
公开(公告)号：US20050038973A1
公开(公告)日：2005-02-17
申请号：US10640855
申请日：2003-08-13
申请人： Masayuki Ito , Fumio Arakawa , Mark Hill
发明人： Masayuki Ito , Fumio Arakawa , Mark Hill
IPC分类号： G06F12/10 , G06F12/08
CPC分类号： G06F12/1027 , G06F2212/652 , G06F2212/681
摘要： In performing address translation from a virtual address space to a physical address space, when the virtual address space is divided into an area (P0), which is subjected to the address translation by TLB, and areas (P1 and P2), which are fixedly mapped to the physical address without being subjected the address translation, future extension of the physical address become difficult. A data processor comprises an address translation unit ATU that receives virtual address output from the CPU and outputs a physical address; the ATU includes a first translation lookaside buffer UTLB, a second translation lookaside buffer DTLB, a control circuit TLB_CTL that selects one of a first and a second translation lookaside buffers and performs address translation in accordance with an area of an address space in the virtual address. Since it is adapted so that the areas (P1 and P2), which are conventionally mapped fixedly by hardware, are subjected to the address translation by the DTLB, it is possible to extend a size of the physical address space later without changing the hardware.
摘要翻译：在从虚拟地址空间进行地址转换到物理地址空间时，当虚拟地址空间被划分成由TLB进行地址转换的区域（P0）和固定地区域（P1和P2）时，映射到物理地址而不受地址转换，物理地址的未来扩展变得困难。数据处理器包括地址转换单元ATU，其接收从CPU输出的虚拟地址并输出物理地址; ATU包括第一翻译后备缓冲器UTLB，第二翻译后备缓冲器DTLB，控制电路TLB_CTL，其根据虚拟地址中的地址空间的区域选择第一和第二翻译后备缓冲器中的一个并执行地址转换。由于适配使得由硬件固定地映射的区域（P1和P2）由DTLB进行地址转换，所以可以在不改变硬件的情况下延长物理地址空间的大小。

7. 发明授权

US06898671B2 Data processor for reducing set-associative cache energy via selective way prediction 有权
标题翻译：数据处理器，用于通过选择性方式预测减少集相关高速缓存能量
公开(公告)号：US06898671B2
公开(公告)日：2005-05-24
申请号：US10083342
申请日：2002-02-27
申请人： Masayuki Ito , Junichi Nishimoto
发明人： Masayuki Ito , Junichi Nishimoto
IPC分类号： G06F12/08 , G06F12/12 , G06F9/28
CPC分类号： G06F12/0864 , G06F12/0855 , G06F2212/1028 , G06F2212/6082 , Y02D10/13
摘要： The data processor has a set-associative cache memory capable of performing associative operation using tag information for an indexed cache line. The cache memory includes way prediction part for performing a selection of a way based on the prediction in parallel with the associative operation, generation part for generating way selection determining information based on the associative operation using the subsequent access address during a penalty cycle caused by a prediction miss of the way prediction part, and control part for making a way selected for the subsequent access address after the penalty cycle on the basis of the way selection determining information. Since a way to be hit at the subsequent cache access can be predetermined during the preceding penalty cycle, the cumulative number of penalty cycles can be reduced.
摘要翻译：数据处理器具有能够使用用于索引的高速缓存行的标签信息执行关联操作的集合关联高速缓存存储器。高速缓冲存储器包括：方法预测部分，用于基于与关联操作并行的预测方式来执行选择方式;生成部分，用于基于使用后续访问地址在由方式预测部分的预测缺失，以及基于方式选择确定信息，在惩罚周期之后为后续访问地址选择的方式的控制部分。由于可以在先前罚球周期期间预定在后续高速缓存访问中被击中的方式，因此可以减少累积罚球次数。

8. 发明授权

US08877393B2 Fuel cell 有权
标题翻译：燃料电池
公开(公告)号：US08877393B2
公开(公告)日：2014-11-04
申请号：US13383084
申请日：2010-05-21
申请人： Hiroaki Takeuchi , Tomohiro Ogawa , Ryouichi Nanba , Takumi Taniguchi , Shinji Jomori , Koichiro Ikeda , Shigeki Hasegawa , Masayuki Ito , Hitoshi Hamada , Naohiro Takeshita
发明人： Hiroaki Takeuchi , Tomohiro Ogawa , Ryouichi Nanba , Takumi Taniguchi , Shinji Jomori , Koichiro Ikeda , Shigeki Hasegawa , Masayuki Ito , Hitoshi Hamada , Naohiro Takeshita
IPC分类号： H01M8/06 , H01M8/04 , H01M8/10 , H01M4/86 , H01M8/24 , H01M8/02
CPC分类号： H01M8/04089 , H01M4/8605 , H01M4/8668 , H01M8/0267 , H01M8/0273 , H01M8/04119 , H01M8/242 , H01M2008/1095 , Y02E60/50
摘要： A fuel cell is disclosed comprising: a power generation layer including an electrolyte membrane, and an anode and a cathode provided on respective surfaces of the electrolyte membrane; a fuel gas flow path layer located on a side of the anode of the power generation layer to supply a fuel gas to the anode while flowing the fuel gas along a flow direction of the fuel gas approximately orthogonal to a stacking direction in which respective layers of the fuel cell are stacked; and an oxidizing gas flow path layer located on a side of the cathode of the power generation layer to supply an oxidizing gas to the cathode while flowing the oxidizing gas along a flow direction of the oxidizing gas opposed to the flow direction of the fuel gas. A power generation area of the fuel cell, in which electric power is generated, has an upstream region including a most upstream position along the flow direction of the fuel gas and a downstream region including a most downstream position along the flow direction of the fuel gas. A midstream region, which is a remaining region of the power generation area other than the upstream region and the downstream region, has higher water vapor transfer resistance between the anode side and the cathode side than the upstream region and the downstream region.
摘要翻译：公开了一种燃料电池，包括：包括电解质膜的发电层和设置在电解质膜的各个表面上的阳极和阴极; 位于所述发电层的阳极侧的燃料气体流路层，用于向所述阳极供给燃料气体，同时使所述燃料气体沿所述燃料气体的流动方向大致垂直于层叠方向燃料电池堆叠; 以及氧化气体流路层，其位于发电层的阴极侧，以向氧化剂气体沿与燃料气体的流动方向相反的氧化气体的流动方向流动而向氧化气体供给氧化气体。燃料电池的产生电力的发电区域沿着燃料气体的流动方向具有包括最上游位置的上游区域和沿着燃料气体的流动方向的包括最下游位置的下游区域。作为上游区域和下游区域以外的发电区域的剩余区域的中游区域，在阳极侧和阴极侧之间比上游区域和下游区域具有更高的水蒸气传递阻力。

9. 发明授权

US08623510B2 Graphite material and method for manufacturing the same 失效
标题翻译：石墨材料及其制造方法
公开(公告)号：US08623510B2
公开(公告)日：2014-01-07
申请号：US12448411
申请日：2007-12-21
申请人： Akiyoshi Takeda , Masayuki Ito
发明人： Akiyoshi Takeda , Masayuki Ito
IPC分类号： C01B31/00 , C01B31/04 , C01B31/30
CPC分类号： H01L23/373 , C04B35/522 , C04B35/532 , C04B35/6303 , C04B35/6316 , C04B2235/3208 , C04B2235/3225 , C04B2235/3232 , C04B2235/3241 , C04B2235/3244 , C04B2235/3251 , C04B2235/3256 , C04B2235/3262 , C04B2235/3272 , C04B2235/3275 , C04B2235/3279 , C04B2235/3289 , C04B2235/3418 , C04B2235/3817 , C04B2235/3826 , C04B2235/3839 , C04B2235/3843 , C04B2235/402 , C04B2235/407 , C04B2235/5436 , C04B2235/602 , C04B2235/6021 , C04B2235/616 , C04B2235/725 , C04B2235/728 , C04B2235/761 , C04B2235/77 , C04B2235/80 , C04B2235/9607 , C22C1/1036 , C22C1/1084 , C22C2001/1073 , H01L2924/0002 , Y10T428/30 , H01L2924/00
摘要： Provided are a graphite material, which has excellent bonding characteristics to semiconductor and efficiently dissipates heat generated from the semiconductor, and a method for manufacturing such material. The graphite material is provided by adding at least two kinds of elements selected from among silicon, zirconium, calcium, titanium, chromium, manganese, iron, cobalt, nickel, calcium, yttrium, niobium, molybdenum, technetium, ruthenium and compounds containing such elements, and by performing heat treatment. The graphite material is characterized in having a thickness of the 112 face of the graphite crystal of 15 nm or more by X-ray diffraction, and an average heat conductivity of 250 W/(m·K) or more in the three directions of the X, Y and Z axes.
摘要翻译：提供了一种石墨材料，其具有优异的半导体结合特性并有效地散发由半导体产生的热量，以及这种材料的制造方法。通过添加选自硅，锆，钙，钛，铬，锰，铁，钴，镍，钙，钇，铌，钼，锝，钌中的至少两种元素来提供石墨材料，以及含有这些元素的化合物，并进行热处理。石墨材料的特征在于，通过X射线衍射，石墨晶体的112面的厚度为15nm以上，平均导热率为250W /（m·K）以上 X，Y和Z轴。

10. 发明授权

US08115790B2 Medium detecting apparatus and image forming apparatus 有权
标题翻译：介质检测装置和图像形成装置
公开(公告)号：US08115790B2
公开(公告)日：2012-02-14
申请号：US11691537
申请日：2007-03-27
申请人： Masayuki Ito
发明人： Masayuki Ito
IPC分类号： G01D15/06 , G01D15/08 , B41J2/325 , B41J2/435
CPC分类号： B41J11/0095
摘要： A medium detecting apparatus and an image forming apparatus are supplied capable of making medium move without hitting sensor lever while skew adjustment or medium setting operation. In the image forming apparatus, a medium hit surface of the sensor lever to detect skew holds inclinations in plural directions and a guider to limit the medium is furnished on the inclined side; or a medium hit surface of the sensor lever to detect skew holds inclinations in plural directions and position detections in movement direction of carriage and in conveyance direction of medium are performed by one sensor; or a sheet guider is further furnished and the sensor lever whose medium hit surface holds inclinations in plural directions is used as a sensor to detect a paper setting; or a hand-operated adjustment print function is further furnished and the sensor lever whose medium hit surface holds inclinations in plural directions is used as a sensor to detect a paper setting.
摘要翻译：提供介质检测装置和图像形成装置，其能够在不偏转调节或介质设置操作的情况下进行介质移动而不会碰到传感器杆。在图像形成装置中，检测偏斜的传感器杆的介质撞击面保持多个方向的倾斜，并且在倾斜侧设置限制介质的导向器; 或传感器杆的中等撞击表面，以检测倾斜保持多个方向的倾斜，并且通过一个传感器执行托架移动方向和介质传送方向上的位置检测; 或者进一步布置纸张引导器，并且使用中等命中表面保持多个方向的倾斜度的传感器杆作为检测纸张设置的传感器; 或者进一步配置手动调节打印功能，并且使用中等命中表面保持多个方向倾斜的传感器杆作为检测纸张设置的传感器。

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