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1. 发明授权

US06864541B2 Semiconductor device having a protruded active region, memory system having the same, and electronic apparatus having the same 有权
标题翻译：具有突出有源区域的半导体器件，具有该有源区域的存储器系统和具有该有源区域的电子设备
公开(公告)号：US06864541B2
公开(公告)日：2005-03-08
申请号：US10072316
申请日：2002-02-08
申请人： Junichi Karasawa , Kunio Watanabe
发明人： Junichi Karasawa , Kunio Watanabe
IPC分类号： H01L21/3205 , H01L21/768 , H01L21/822 , H01L21/8244 , H01L23/52 , H01L27/04 , H01L27/11 , H01L29/76
CPC分类号： H01L27/1104 , Y10S257/903
摘要： A semiconductor device is provided with an SRAM memory cell. The semiconductor device includes a first gate-gate electrode layer, a second gate-gate electrode layer, a first drain-drain wiring layer, a second drain-drain wiring layer, a first drain-gate wiring layer and second drain-gate wiring layers. The first drain-gate wiring layer and an upper layer and a lower layer of the second drain-gate wiring layer are located in different layers, respectively. A first protruded active region is provided in a manner to protrude from an end portion of the first active region.
摘要翻译：半导体器件设置有SRAM存储单元。半导体器件包括第一栅极 - 栅极电极层，第二栅极 - 栅极电极层，第一漏极 - 漏极布线层，第二漏极 - 漏极布线层，第一漏极 - 栅极布线层和第二漏极 - 栅极布线层。第一漏极 - 栅极布线层和第二漏极 - 栅极布线层的上层和下层分别位于不同的层中。第一突出的有源区域以从第一有源区域的端部突出的方式设置。

2. 发明授权

US06815777B2 Semiconductor device, memory system and electronic apparatus 有权
标题翻译：半导体器件，存储器系统和电子设备
公开(公告)号：US06815777B2
公开(公告)日：2004-11-09
申请号：US10092393
申请日：2002-03-05
申请人： Junichi Karasawa , Kunio Watanabe
发明人： Junichi Karasawa , Kunio Watanabe
IPC分类号： H01L2976
CPC分类号： H01L27/11 , H01L27/1104
摘要： A semiconductor device is provided with a memory cell. The semiconductor device includes a first gate-gate electrode layer, a second gate-gate electrode layer, a first drain-drain wiring layer, a second drain-drain wiring layer, a first drain-gate wiring layer and a second drain-gate wiring layer. The first drain-gate wiring layer and an upper layer and a lower layer of the second drain-gate wiring layer are located in different layers, respectively.
摘要翻译：半导体器件设置有存储单元。半导体器件包括第一栅极 - 栅极电极层，第二栅极 - 栅极电极层，第一漏极 - 漏极布线层，第二漏极 - 漏极布线层，第一漏极 - 栅极布线层和第二漏极 - 栅极布线层。第一漏极 - 栅极布线层和第二漏极 - 栅极布线层的上层和下层分别位于不同的层中。

3. 发明授权

US06747322B2 Semiconductor device, memory system and electronic apparatus 有权
标题翻译：半导体器件，存储器系统和电子设备
公开(公告)号：US06747322B2
公开(公告)日：2004-06-08
申请号：US10154423
申请日：2002-05-21
申请人： Junichi Karasawa , Kunio Watanabe
发明人： Junichi Karasawa , Kunio Watanabe
IPC分类号： H01L2976
CPC分类号： H01L27/1104
摘要： A semiconductor device having a memory cell including first and second load transistors, first and second driver transistors, and first and second transfer transistors. The semiconductor device includes first and second gate—gate electrode layers, first and second drain—drain wiring layers, and first and second drain-gate wiring layers. The first drain-gate wiring layer and the second drain-gate wiring layer are located in different layers. The first drain-gate wiring layer is located below the first drain—drain wiring layer, and the second drain-gate wiring layer is located in above the first drain—drain wiring layer. This structure provides a semiconductor device that has reduced cell area. The invention also provides a memory system and electronic apparatus that include the above semiconductor device.
摘要翻译：具有包括第一和第二负载晶体管，第一和第二驱动晶体管以及第一和第二转移晶体管的存储单元的半导体器件。半导体器件包括第一和第二栅极 - 栅极电极层，第一和第二漏极 - 漏极布线层以及第一和第二漏极 - 栅极布线层。第一漏极 - 栅极布线层和第二漏极 - 栅极布线层位于不同的层中。第一漏极 - 栅极布线层位于第一漏极 - 漏极布线层的下方，第二漏极 - 栅极布线层位于第一漏极 - 漏极布线层的上方。该结构提供了具有减小的单元面积的半导体器件。本发明还提供了包括上述半导体器件的存储器系统和电子设备。

4. 发明授权

US06320234B1 Semiconductor memory device and method for manufacturing the same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US06320234B1
公开(公告)日：2001-11-20
申请号：US09450102
申请日：1999-11-29
申请人： Junichi Karasawa , Kunio Watanabe , Takashi Kumagai
发明人： Junichi Karasawa , Kunio Watanabe , Takashi Kumagai
IPC分类号： H01L2976
CPC分类号： H01L27/105 , H01L27/1052
摘要： A semiconductor device has a semiconductor substrate having a peripheral circuit area and a memory cell area. A border region having a well of a first conductivity is formed between the peripheral circuit area and the memory cell area. A well of a second conductivity is formed in the peripheral circuit area. The well in the peripheral circuit area is in contact with the border region but not in contact with the memory cell area. Dummy transistors are formed in the border region. The dummy transistors are arranged with substantially the same transistor forming density as that of the memory cell area.
摘要翻译：半导体器件具有具有外围电路区域和存储单元区域的半导体衬底。在外围电路区域和存储单元区域之间形成具有第一导电性阱的边界区域。在外围电路区域形成第二导电性阱。外围电路区域中的阱与边界区域接触，但不与存储单元区域接触。在边界区域形成虚拟晶体管。虚拟晶体管被布置成与存储单元区域基本上相同的晶体管形成密度。

5. 发明授权

US06300229B1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06300229B1
公开(公告)日：2001-10-09
申请号：US09563130
申请日：2000-05-02
申请人： Kazuo Tanaka , Takashi Kumagai , Junichi Karasawa , Kunio Watanabe
发明人： Kazuo Tanaka , Takashi Kumagai , Junichi Karasawa , Kunio Watanabe
IPC分类号： H01L2120
CPC分类号： H01L27/11 , H01L21/28518 , H01L21/76895 , H01L21/76897 , H01L27/1104
摘要： A method of manufacturing a semiconductor device comprising the following steps: forming first, second, and third wiring layers on a semiconductor substrate; forming first, second, and third cover dielectric layers for covering these wiring layers; forming a first impurity diffusion layer of a P type and a second impurity diffusion layer of an N type in an active region, and forming a third impurity diffusion layer of a P type and a fourth impurity diffusion layer of an N type in an active region; self-alignably forming a first local wiring layer for connecting the first impurity diffusion layer with the second wiring layer, and self-alignably forming a second local wiring layer for connecting the fourth impurity diffusion layer with the third wiring layer; in an interlayer dielectric layer, self-alignably forming a first contact hole by using the first and third cover dielectric layers as masking layers, and self-alignably forming a second contact hole by using the second cover dielectric layer as a masking layer; and forming fourth and fifth wiring layers in these contact holes, respectively.
摘要翻译：一种制造半导体器件的方法，包括以下步骤：在半导体衬底上形成第一，第二和第三布线层; 形成用于覆盖这些布线层的第一，第二和第三覆盖电介质层; 在有源区中形成P型和N型的第二杂质扩散层的第一杂质扩散层，在有源区中形成P型的第三杂质扩散层和N型的第四杂质扩散层 ; 自对准地形成用于将第一杂质扩散层与第二布线层连接的第一局部布线层，并自对准地形成用于将第四杂质扩散层与第三布线层连接的第二局部布线层; 在层间电介质层中，通过使用第一和第三覆盖电介质层作为掩蔽层自对准地形成第一接触孔，并且通过使用第二覆盖电介质层作为掩蔽层自对准地形成第二接触孔; 并且在这些接触孔中分别形成第四和第五布线层。

6. 发明授权

US06730974B2 Semiconductor devices, memory systems and electronic apparatuses with improved latch up suppression 有权
标题翻译：具有改进的闭锁抑制的半导体器件，存储器系统和电子设备
公开(公告)号：US06730974B2
公开(公告)日：2004-05-04
申请号：US10150498
申请日：2002-05-16
申请人： Junichi Karasawa , Kunio Watanabe
发明人： Junichi Karasawa , Kunio Watanabe
IPC分类号： H01L2976
CPC分类号： H01L27/1104 , Y10S257/903
摘要： Semiconductor devices are provided that include a memory cell having load transistors, driver transistors, and transfer transistors. The semiconductor device has a first element-forming region that can be provided in, for example, a p-well region. The first element-forming region can include includes a first active region, a second active region, a third active region, a fourth active region and a fifth active region. The third active region, the fourth active region and the fifth active region can be provided between the first active region and the second active region. The first active region and the second active region can be continuous with the third active region, the fourth active region and the fifth active region, respectively. Thus, semiconductor devices can be provided having element-forming regions that can be readily formed. Memory systems and electronic equipment that include such semiconductor devices can also be provided.
摘要翻译：提供了包括具有负载晶体管，驱动晶体管和转移晶体管的存储单元的半导体器件。半导体器件具有第一元件形成区域，其可以设置在例如p阱区域中。第一元件形成区域可以包括第一有源区，第二有源区，第三有源区，第四有源区和第五有源区。第三有源区，第四有源区和第五有源区可以设置在第一有源区和第二有源区之间。第一有源区和第二有源区可以分别与第三有源区，第四有源区和第五有源区连续。因此，可以提供具有易于形成的元件形成区域的半导体器件。还可以提供包括这种半导体器件的存储器系统和电子设备。

7. 发明授权

US06664603B2 Semiconductor device, memory system and electronic apparatus 失效
公开(公告)号：US06664603B2
公开(公告)日：2003-12-16
申请号：US10153430
申请日：2002-05-21
申请人： Junichi Karasawa , Kunio Watanabe
发明人： Junichi Karasawa , Kunio Watanabe
IPC分类号： H01L2976
CPC分类号： H01L27/1104 , Y10S257/903
摘要： A semiconductor device having a memory cell including first and second load transistors, first and second driver transistors, and first and second transfer transistors. The semiconductor device includes a first gate-gate electrode layer and a first drain-gate wiring layer. A distance L1 between the edges of the first drain-gate wiring layer and an active region of the first driver transistor is greater than or equal to a distance L2 between the first drain-gate wiring layer and an active region of the first load transistor. This structure provides semiconductor devices in which memory cells having desired characteristics can be readily fabricated. The invention also provides memory systems and electronic apparatuses which include the above semiconductor devices.

8. 发明授权

US06243286B1 Semiconductor memory device and method of fabricating the same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US06243286B1
公开(公告)日：2001-06-05
申请号：US09361095
申请日：1999-07-26
申请人： Takashi Kumagai , Junichi Karasawa , Kazuo Tanaka , Kunio Watanabe
发明人： Takashi Kumagai , Junichi Karasawa , Kazuo Tanaka , Kunio Watanabe
IPC分类号： G11C1100
CPC分类号： H01L27/11 , H01L27/1104 , Y10S257/903
摘要： An SRAM comprises first, second and third conductive layers. The first conductive layer is a gate electrode for a first load transistor and a first driver transistor. The second conductive layer branches from the first conductive layer on a field oxide region and is electrically connected to a second driver transistor active region. The third conductive layer is a gate electrode for a second load transistor and a second driver transistor. The third conductive layer is electrically connected to a first load transistor active region. The width of part of the second conductive layer on the field oxide region is less than the width of the first conductive layer.
摘要翻译： SRAM包括第一，第二和第三导电层。第一导电层是用于第一负载晶体管和第一驱动晶体管的栅电极。第二导电层在场氧化物区域上从第一导电层分支并且电连接到第二驱动晶体管有源区。第三导电层是用于第二负载晶体管的栅电极和第二驱动晶体管。第三导电层电连接到第一负载晶体管有源区。场氧化物区域上的第二导电层的一部分的宽度小于第一导电层的宽度。

9. 发明授权

US6081016A CMOS device with improved wiring density 有权
标题翻译：具有改善布线密度的CMOS器件
公开(公告)号：US6081016A
公开(公告)日：2000-06-27
申请号：US282035
申请日：1999-03-30
申请人： Kazuo Tanaka , Takashi Kumagai , Junichi Karasawa , Kunio Watanabe
发明人： Kazuo Tanaka , Takashi Kumagai , Junichi Karasawa , Kunio Watanabe
IPC分类号： H01L21/28 , H01L21/285 , H01L21/60 , H01L21/768 , H01L21/8238 , H01L21/8244 , H01L27/092 , H01L27/11 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/11 , H01L21/28518 , H01L21/76895 , H01L21/76897 , H01L27/1104
摘要： A method of manufacturing a semiconductor device comprising the following steps: forming first, second, and third wiring layers on a semiconductor substrate; forming first, second, and third cover dielectric layers for covering these wiring layers; forming a first impurity diffusion layer of a P type and a second impurity diffusion layer of an N type in an active region, and forming a third impurity diffusion layer of a P type and a fourth impurity diffusion layer cf an N type in an active region; self-alignably forming a first local wiring layer for connecting the first impurity diffusion layer with the second wiring layer, and self-alignably forming a second local wiring layer for connecting the fourth impurity diffusion layer with the third wiring layer; in an interlayer dielectric layer, self-alignably forming a first contact hole by using the first and third cover dielectric layers as masking layers, and self-alignably forming a second contact hole by using the second cover dielectric layer as a masking layer; and forming fourth and fifth wiring layers in these contact holes, respectively.
摘要翻译：一种制造半导体器件的方法，包括以下步骤：在半导体衬底上形成第一，第二和第三布线层; 形成用于覆盖这些布线层的第一，第二和第三覆盖电介质层; 在有源区中形成P型和N型的第二杂质扩散层的第一杂质扩散层，在有源区中形成N型的P型和第四杂质扩散层的第三杂质扩散层 ; 自对准地形成用于将第一杂质扩散层与第二布线层连接的第一局部布线层，并自对准地形成用于将第四杂质扩散层与第三布线层连接的第二局部布线层; 在层间电介质层中，通过使用第一和第三覆盖电介质层作为掩蔽层自对准地形成第一接触孔，并且通过使用第二覆盖电介质层作为掩蔽层自对准地形成第二接触孔; 并且在这些接触孔中分别形成第四和第五布线层。

10. 发明授权

US6034432A Thin film transistors and connecting structure for semiconductors and a method of manufacturing the same 失效
标题翻译：薄膜晶体管和半导体的连接结构及其制造方法
公开(公告)号：US6034432A
公开(公告)日：2000-03-07
申请号：US750760
申请日：1997-03-10
申请人： Junichi Karasawa , Kunio Watanabe
发明人： Junichi Karasawa , Kunio Watanabe
IPC分类号： H01L21/8244 , H01L27/11 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L27/11 , H01L27/1108 , Y10S257/903
摘要： A metallic layer (10), a thin-film first polycrystalline silicon layer (14), a first contact hole for connecting the metallic layer and first polycrystalline silicon layer, a second polycrystalline silicon layer (18) which becomes an etching stopper layer for the prevention of penetration in the first contact hole area, and a second contact hole which connects the second polycrystalline silicon layer and the first polycrystalline silicon layer are included. P-type impurities are introduced into the first polycrystalline silicon layer, and the second polycrystalline silicon layer is non-doped in the first contact hole area. By a heating step, the P-type impurities in the first polycrystalline silicon layer are diffused to the second polycrystalline silicon layer. The second polycrystalline silicon layer is N-type in a memory cell area. An insulating layer may be formed into a concave shape in the first contact hole area to lower the height of the first polycrystalline silicon layer in the first contact hole area.
摘要翻译： PCT No.PCT / JP96 / 01047 Sec。 371日期1997年3月10日 102（e）1997年3月10日PCT PCT 1996年4月17日PCT公布。第WO96 / 33512号公报日期：1996年10月24日金属层（10），薄膜第一多晶硅层（14），用于连接金属层和第一多晶硅层的第一接触孔，第二多晶硅层（18）用于防止在第一接触孔区域中穿透的蚀刻阻挡层，以及连接第二多晶硅层和第一多晶硅层的第二接触孔。 P型杂质被引入到第一多晶硅层中，并且第二多晶硅层在第一接触孔区域中未被掺杂。通过加热步骤，第一多晶硅层中的P型杂质扩散到第二多晶硅层。第二多晶硅层是存储单元区域中的N型。绝缘层可以在第一接触孔区域中形成为凹形，以降低第一接触孔区域中的第一多晶硅层的高度。

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