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    • 5. 发明授权
    • PLL circuit
    • PLL电路
    • US06441661B1
    • 2002-08-27
    • US09720658
    • 2000-12-28
    • Hiroshi AokiShiro SuzukiJunichi HorigomeTakayoshi ChibaShigeo Yamaguchi
    • Hiroshi AokiShiro SuzukiJunichi HorigomeTakayoshi ChibaShigeo Yamaguchi
    • H03L706
    • G11B20/1024
    • An A/D converter (30) samples an analog signal synchronously with a sampling clock from a VCO (70). These sampled values are stored in a shift register (410). A code judging section (420) detects the positive/negative sign pattern (time-series code pattern) of the sampled values held in storage elements (S0 to S5) of the shift register (410) and stores the sampled values in predetermined register (431 to 434) according to the detected sign pattern. According to this, a calculating section (430) determines the phase difference between the analog signal and the sampling clock. The phase difference is fed to a VCO (70) through a D/A converter (50) and a loop filter (60).
    • A / D转换器(30)与来自VCO(70)的采样时钟同步地采样模拟信号。 这些采样值被存储在移位寄存器(410)中。 代码判定部分(420)检测保持在移位寄存器(410)的存储元件(S0至S5)中的采样值的正/负符号模式(时间序列码模式),并将采样值存储在预定寄存器 431〜434)。 据此,计算部(430)确定模拟信号和采样时钟之间的相位差。 相位差通过D / A转换器(50)和环路滤波器(60)馈送到VCO(70)。
    • 8. 发明授权
    • Information reproducing apparatus and reproducing method
    • 信息再现装置和再现方法
    • US06317471B1
    • 2001-11-13
    • US09059477
    • 1998-04-13
    • Junichi HorigomeShigeo YamaguchiTakayoshi Chiba
    • Junichi HorigomeShigeo YamaguchiTakayoshi Chiba
    • H03D100
    • G11B20/10296G11B20/1426
    • An ACS of a Viterbi decoder generates status data that an SMU represents a status transition corresponding to the maximum likelihood status transition selected corresponding to each read clock pulse. A merge block generates decoded data corresponding to status data. A timing generator generates timings of a leading edge and a trailing edge of a reproduced RF signal corresponding to status data. A PEC generates a phase error signal PE corresponding to a reproduced signal value sampled at these the timings (namely, sampling values of an A/D converter). With the phase error signal PE, a VCO is controlled. The memory length of the SMU that generates the timings is smaller than the memory length for a decoding process. One of the memory lengths can be selected depending on whether data is reproduced from a header area or a data area.
    • 维特比解码器的ACS产生状态数据,SMU表示对应于对应于每个读时钟脉冲选择的最大似然状态转变的状态转变。 合并块产生与状态数据相对应的解码数据。 定时发生器产生对应于状态数据的再现RF信号的前沿和后沿的定时。 PEC产生与在这些定时(即A / D转换器的采样值)采样的再生信号值对应的相位误差信号PE。 利用相位误差信号PE,控制VCO。 生成定时的SMU的存储器长度小于解码处理的存储器长度。 可以根据从头部区域还是数据区域再现数据来选择存储器长度之一。