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    • 1. 发明授权
    • Data path reset circuit using clock enable signal, reset method, and semiconductor memory device including the data path reset circuit and adopting the reset method
    • 使用时钟使能信号,复位方式的数据路径复位电路和包括数据路径复位电路的半导体存储器件,并采用复位方法
    • US06826114B2
    • 2004-11-30
    • US10624783
    • 2003-07-22
    • Jung-bae LeeWon-chang Jung
    • Jung-bae LeeWon-chang Jung
    • G11C800
    • G11C7/1057G11C7/1051G11C7/1069G11C7/1078G11C7/1096
    • Provided are a reset circuit of a data path using a clock enable signal, a reset method and a semiconductor memory device having the reset circuit. The reset circuit includes an external voltage detector and a second reset signal generator, in which the second reset signal is used to reset a block related to a data path of the semiconductor memory device. The external voltage detector detects the level of an external voltage and generates a first reset signal. The second reset signal generator performs a logical sum of an external signal, which is externally input, and the first reset signal, and generates a second reset signal. The first reset signal is used to reset blocks other than the blocks related to the data path. The external signal is a clock enable signal. In the soft reset, the blocks related to the data path are reset using the external signal which is applied at a certain level. Thus, data conflicts or ineffective data can be prevented in executing operations according to the read/write commands which are applied after the soft reset.
    • 提供了使用时钟使能信号的数据路径的复位电路,复位方法和具有复位电路的半导体存储器件。 复位电路包括外部电压检测器和第二复位信号发生器,其中第二复位信号用于复位与半导体存储器件的数据路径有关的块。 外部电压检测器检测外部电压的电平并产生第一复位信号。 第二复位信号发生器执行外部输入的外部信号与第一复位信号的逻辑和,并产生第二复位信号。 第一复位信号用于复位与数据路径相关的块以外的块。 外部信号是时钟使能信号。 在软复位中,与数据通路相关的模块使用外部信号进行复位,该外部信号以一定的电平施加。 因此,根据在软复位之后应用的读/写命令执行操作时,可以防止数据冲突或无效数据。
    • 6. 发明授权
    • DRAM partial refresh circuits and methods
    • DRAM部分刷新电路和方法
    • US06982917B2
    • 2006-01-03
    • US10192406
    • 2002-07-10
    • Yun-sang LeeWon-chang Jung
    • Yun-sang LeeWon-chang Jung
    • G11C7/00
    • G11C11/406
    • Circuits and methods for refreshing memory banks in a DRAM are provided. A refresh circuit is provided in a DRAM having at least one memory bank and a plurality of word lines connected to memory locations in the memory bank. The word lines are subdivided into first and second groups of subword lines. The refresh circuit includes a delay circuit, a first driving circuit, and a second driving circuit. The delay circuit receives a refresh signal and outputs a delayed refresh signal a predetermined time delay later. The first driving circuit responds to the refresh signal by driving word lines in the first group of subword lines and the second driving circuit responds to the delayed refresh signal by driving word lines in the second group of subword lines.
    • 提供了用于刷新DRAM中的存储体的电路和方法。 在具有至少一个存储体和连接到存储体中的存储器位置的多条字线的DRAM中提供刷新电路。 字线被细分为第一和第二组子字线。 刷新电路包括延迟电路,第一驱动电路和第二驱动电路。 延迟电路接收刷新信号并且稍后在预定的时间延迟中输出延迟的刷新信号。 第一驱动电路通过驱动第一组子字线中的字线来响应刷新信号,并且第二驱动电路通过驱动第二组子字线中的字线来响应延迟的刷新信号。
    • 7. 发明授权
    • Integrated circuit memory devices having efficient column select signal generation during normal and refresh modes of operation and methods of operating same
    • 在正常和刷新操作模式期间产生有效的列选择信号的集成电路存储器件及其操作方法
    • US06819623B2
    • 2004-11-16
    • US10392413
    • 2003-03-19
    • Won-chang Jung
    • Won-chang Jung
    • G11C808
    • G11C11/406G11C11/4087
    • An integrated circuit memory device includes an XY array of memory cell sub-blocks and row and column decoder circuitry that is electrically coupled to the array. The array includes first and second offset grids of sub-word line driver control circuits therein, with each of the sub-word line driver control circuits configured to selectively activate a pair of the memory cell sub-blocks in response to a respective pair of active row and column select signals. In order to improve power consumption requirements when switching back and fourth between normal and refresh modes of operation, the row and column decoder circuitry is configured to drive a selected one of a plurality of row select lines associated with the first grid with an asserted row select signal and a plurality of column select lines associated with the second grid with asserted column select signals during a write operation.
    • 集成电路存储器件包括存储单元子块的XY阵列和电耦合到阵列的行和列解码器电路。 阵列包括其中的子字线驱动器控制电路的第一和第二偏移栅格,其中每个子字线驱动器控制电路被配置为响应于相应的一对有效的选择性地激活一对存储器单元子块 行和列选择信号。 为了在正常操作和刷新操作模式之间切换回切换和第四切换时提高功耗要求,行和列解码器电路被配置为用断言的行选择来驱动与第一格栅相关联的多个行选择线中的所选择的一行 信号以及在写入操作期间与具有断言的列选择信号的第二格栅相关联的多个列选择线。