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1. 发明授权

US06768199B2 Flip chip type semiconductor device and method of fabricating the same 失效
标题翻译：倒装芯片型半导体器件及其制造方法
公开(公告)号：US06768199B2
公开(公告)日：2004-07-27
申请号：US09974025
申请日：2001-10-10
申请人： Jung-Lim Yoon , Jong-Hyon Ahn , Chang-Hun Lee
发明人： Jung-Lim Yoon , Jong-Hyon Ahn , Chang-Hun Lee
IPC分类号： H01L2348
CPC分类号： H01L24/10 , H01L23/5258 , H01L23/528 , H01L24/13 , H01L2224/0401 , H01L2224/05124 , H01L2224/05147 , H01L2224/05181 , H01L2224/05572 , H01L2224/13 , H01L2224/13022 , H01L2224/13099 , H01L2924/0002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01073 , H01L2924/01078 , H01L2924/01082 , H01L2924/04953 , H01L2924/12042 , H01L2924/14 , H01L2924/181 , H01L2224/05552 , H01L2924/00 , H01L2924/00014
摘要： A flip chip type semiconductor device comprises at least one first metal line and at least a pair of second metal lines formed in the passivation layer, an aluminum pad covering the first metal line, an aluminum fuse covering the pair of second metal lines adjacent to each other and the passivation layer therebetween, and an under-bump metal layer pattern and a bump formed on the aluminum pad in order. The first and second metal lines are formed respectively in first and second grooves by using a damascene process after forming first and second grooves in the passivation layer.
摘要翻译：倒装芯片型半导体器件包括至少一个第一金属线和形成在钝化层中的至少一对第二金属线，覆盖第一金属线的铝焊盘，覆盖与每个第二金属线相邻的一对第二金属线的铝保险丝其它和其间的钝化层，以及凸起下方的金属层图案和形成在铝焊盘上的凸块。在钝化层中形成第一和第二凹槽之后，通过使用镶嵌工艺分别在第一和第二凹槽中形成第一和第二金属线。

2. 发明授权

US06890820B2 Method of fabricating FLASH memory devices 有权
标题翻译：制造闪速存储器件的方法
公开(公告)号：US06890820B2
公开(公告)日：2005-05-10
申请号：US10645049
申请日：2003-08-21
申请人： Jung-Lim Yoon , Jae-Min Yu , Chang-Rok Moon
发明人： Jung-Lim Yoon , Jae-Min Yu , Chang-Rok Moon
IPC分类号： H01L21/28 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H10L21/336
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115
摘要： A method of fabricating split gate type FLASH memory device comprises forming trench device isolation layers in a substrate to define a plurality of parallel first active regions. A gate insulation pattern, a conductive pattern and a hard mask pattern, which are sequentially stacked, are formed to have sidewalls aligned to sidewalls of the trench device isolation layer. Along each of the first active regions, the hard mask pattern is removed at regular intervals to expose a top of the conductive pattern. An oxide pattern is formed on the exposed top of the conductive pattern and the hard mask pattern is removed. Using the oxide pattern as an etch mask, the conductive pattern is etched to form floating gate patterns arranged over each of the first active regions at regular intervals. Tunnel oxide layers are formed on sidewalls of the floating gate patterns. A plurality of control gate electrodes are formed to cross over the first active regions. The control gate electrodes are disposed on the floating gate patterns.
摘要翻译：制造分离栅型闪存器件的方法包括在衬底中形成沟槽器件隔离层以限定多个平行的第一有源区。依次层叠的栅极绝缘图案，导电图案和硬掩模图案被形成为具有与沟槽器件隔离层的侧壁对准的侧壁。沿着每个第一有源区域，以规则的间隔去除硬掩模图案以暴露导电图案的顶部。在导电图案的暴露顶部上形成氧化物图案，并且去除硬掩模图案。使用氧化物图案作为蚀刻掩模，蚀刻导电图案以形成以规则的间隔布置在每个第一有源区域上的浮置栅极图案。隧道氧化物层形成在浮动栅极图案的侧壁上。形成多个控制栅电极以跨过第一有源区。控制栅电极设置在浮栅图案上。

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