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    • 3. 发明申请
    • PRE-DISTORTION APPARATUS OF POWER AMPLIFIER AND METHOD THEREOF
    • 功率放大器的预失真装置及其方法
    • US20110063026A1
    • 2011-03-17
    • US12883580
    • 2010-09-16
    • Jae-Ho JUNGGweon-Do JoYoung-Hoon KimJung-Hoon OhKwang-Chun Lee
    • Jae-Ho JUNGGweon-Do JoYoung-Hoon KimJung-Hoon OhKwang-Chun Lee
    • H03F1/26
    • H03F1/3247H03F1/0266H03F3/189H03F3/24H03F2201/3233
    • A pre-distortion apparatus of a power amplifier includes: a pre-distortion unit configured to generate a pre-distorted signal of an input signal by calculating a magnitude of the input signal and outputting a complex correction coefficient corresponding to the calculated magnitude of the input signal, and provide the generated pre-distorted signal as an input of the power amplifier; and a complex correct coefficient update unit configured to generate an error signal by comparing an output signal of the power amplifier with the input signal and updating the complex correction coefficient to minimize a magnitude of the generated error signal, wherein the pre-distortion unit provides a constant bias value corresponding to the magnitude of the input signal as a bias of the power amplifier while updating the complex correction coefficient.
    • 功率放大器的预失真装置包括:预失真单元,被配置为通过计算输入信号的幅度来产生输入信号的预失真信号,并输出与所计算的输入的幅度相对应的复数校正系数 信号,并且将生成的预失真信号提供给功率放大器的输入; 以及复数正确系数更新单元,其被配置为通过将所述功率放大器的输出信号与所述输入信号进行比较来生成误差信号,并更新所述复数校正系数以最小化所生成的误差信号的幅度,其中所述预失真单元提供 对应于作为功率放大器的偏置的输入信号的大小的恒定偏置值,同时更新复数校正系数。
    • 5. 发明申请
    • Fast locking phase locked loop
    • 快锁锁相环
    • US20070285132A1
    • 2007-12-13
    • US11789330
    • 2007-04-24
    • Jung-Hoon Oh
    • Jung-Hoon Oh
    • G01R25/00
    • H03L7/089H03D13/004H03L7/087H03L7/0898H03L7/095H03L7/107H03L7/18
    • A fast locking phase locked loop includes a first phase frequency detector (PFD), a second PFD, a lock detector, an up-signal output unit, a down-signal output unit, a selective charge pump, a loop filter, and a voltage-controlled oscillator (VCO). The first PFD outputs a first up-signal and a first down-signal. The second PFD outputs a second up-signal and a second down-signal. The lock detector outputs an inverted lock signal. The selective charge pump outputs a pumping current. The loop filter generates a control voltage in response to the pumping current. The VCO generates the external clock signal having a frequency determined in accordance with the control voltage. The PLL has a faster locking time because the PFDs included in the PLL are capable of detecting a phase difference in a missing edge.
    • 快速锁定锁相环包括第一相位频率检测器(PFD),第二PFD,锁定检测器,上行信号输出单元,降低信号输出单元,选择性电荷泵,环路滤波器和电压 控制振荡器(VCO)。 第一PFD输出第一上升信号和第一下降信号。 第二PFD输出第二上升信号和第二下降信号。 锁定检测器输出反向锁定信号。 选择性电荷泵输出泵浦电流。 环路滤波器响应于泵浦电流产生控制电压。 VCO产生具有根据控制电压确定的频率的外部时钟信号。 PLL具有更快的锁定时间,因为PLL中包含的PFD能够检测到缺失边缘的相位差。
    • 9. 发明授权
    • Fast locking phase locked loop for synchronization with an input signal
    • 快速锁定锁相环,用于与输入信号同步
    • US07538591B2
    • 2009-05-26
    • US11789330
    • 2007-04-24
    • Jung-Hoon Oh
    • Jung-Hoon Oh
    • H03L7/06
    • H03L7/089H03D13/004H03L7/087H03L7/0898H03L7/095H03L7/107H03L7/18
    • A fast locking phase locked loop includes a first phase frequency detector (PFD), a second PFD, a lock detector, an up-signal output unit, a down-signal output unit, a selective charge pump, a loop filter, and a voltage-controlled oscillator (VCO). The first PFD outputs a first up-signal and a first down-signal. The second PFD outputs a second up-signal and a second down-signal. The lock detector outputs an inverted lock signal. The selective charge pump outputs a pumping current. The loop filter generates a control voltage in response to the pumping current. The VCO generates the external clock signal having a frequency determined in accordance with the control voltage. The PLL has a faster locking time because the PFDs included in the PLL are capable of detecting a phase difference in a missing edge.
    • 快速锁定锁相环包括第一相位频率检测器(PFD),第二PFD,锁定检测器,上行信号输出单元,降低信号输出单元,选择性电荷泵,环路滤波器和电压 控制振荡器(VCO)。 第一PFD输出第一上升信号和第一下降信号。 第二PFD输出第二上升信号和第二下降信号。 锁定检测器输出反相锁定信号。 选择性电荷泵输出泵浦电流。 环路滤波器响应于泵浦电流产生控制电压。 VCO产生具有根据控制电压确定的频率的外部时钟信号。 PLL具有更快的锁定时间,因为PLL中包含的PFD能够检测到缺失边缘的相位差。