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1. 发明授权

US07368379B2 Multi-layer interconnect structure for semiconductor devices 有权
标题翻译：用于半导体器件的多层互连结构
公开(公告)号：US07368379B2
公开(公告)日：2008-05-06
申请号：US11197009
申请日：2005-08-04
申请人： Jung-Chih Tsao , Kei-Wei Chen , Yu-Ku Lin , Chyi S Chern
发明人： Jung-Chih Tsao , Kei-Wei Chen , Yu-Ku Lin , Chyi S Chern
IPC分类号： H01L21/3205
CPC分类号： C25D5/10 , C25D5/18 , C25D7/123 , H01L21/2885 , H01L21/76847 , H01L21/76877
摘要： An interconnect structure for a semiconductor device and its method of manufacture is provided. The interconnect structure includes a multi-layer structure having one or more stress-relief layers. In an embodiment, stress-relief layers are positioned between layers of electroplated copper or other conductive material. The stress-relief layer counteracts stress induced by the conductive material and helps prevent or reduce a pull-back void. For an interconnect structure using electroplated copper, the stress-relief layer may be formed by temporarily reducing the electroplating current, thereby causing a thin film of copper having a larger grain size to be formed between other layers of copper. The larger grain size typically exhibits more of a compressive stress than copper with a smaller grain size. The stress relief layer may also be formed of other materials, such as SIP-Cu, Ta, SiC, or the like.
摘要翻译：提供了半导体器件的互连结构及其制造方法。互连结构包括具有一个或多个应力消除层的多层结构。在一个实施例中，应力消除层位于电镀铜或其它导电材料的层之间。应力消除层抵消由导电材料引起的应力，并有助于防止或减少拉回空隙。对于使用电镀铜的互连结构，可以通过暂时减少电镀电流来形成应力消除层，从而在其它铜层之间形成具有较大晶粒尺寸的铜的薄膜。较大的晶粒尺寸通常表现出比具有较小晶粒尺寸的铜更多的压缩应力。应力消除层也可以由其它材料形成，例如SIP-Cu，Ta，SiC等。

2. 发明申请

US20100230815A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20100230815A1
公开(公告)日：2010-09-16
申请号：US12785618
申请日：2010-05-24
申请人： Jung-Chih Tsao , Kei-Wei Chen , Yu-Ku Lin
发明人： Jung-Chih Tsao , Kei-Wei Chen , Yu-Ku Lin
IPC分类号： H01L23/522 , H01L23/48
CPC分类号： H01L23/5226 , H01L21/76805 , H01L21/76807 , H01L21/76832 , H01L21/76844 , H01L21/76846 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： Semiconductor devices and methods for fabricating the same. An exemplary device includes a substrate, a dielectric layer, a protection layer, and a conformal barrier layer. The dielectric layer overlies the substrate and comprises an opening. The opening comprises a lower portion and a wider upper portion, exposing parts of the substrate. The bottoms of the upper portion act as shoulders of the opening. The protection layer overlies at least one shoulder of the opening. The conformal barrier layer is disposed in the opening and overlies the protection layer and the dielectric layer, wherein etching resistance of the protection layer against inert-gas plasma is higher than that of the barrier layer.
摘要翻译：半导体器件及其制造方法。示例性器件包括衬底，电介质层，保护层和共形阻挡层。电介质层覆盖在衬底上并且包括开口。开口包括下部和较宽的上部，暴露基底的部分。上部的底部作为开口的肩部。保护层覆盖开口的至少一个肩部。共形阻挡层设置在开口中并覆盖保护层和电介质层，其中保护层对惰性气体等离子体的耐蚀性高于阻挡层的抗蚀性。

3. 发明授权

US07417321B2 Via structure and process for forming the same 有权
标题翻译：通过结构及其形成方法
公开(公告)号：US07417321B2
公开(公告)日：2008-08-26
申请号：US11323484
申请日：2005-12-30
申请人： Jung-Chih Tsao , Kei-Wei Chen , Ying-Jing Lu , Yu-Sheng Wang , Yu-Ku Lin
发明人： Jung-Chih Tsao , Kei-Wei Chen , Ying-Jing Lu , Yu-Sheng Wang , Yu-Ku Lin
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76844 , H01L21/76805 , H01L21/76846 , H01L21/76865 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Via structure and process flow for interconnection in a semiconductor product. A bottom metal layer is provided to represent a connection layer in the semiconductor product. An isolation layer on the bottom metal layer comprises a via hole exposing a portion of the bottom metal layer. The via hole comprises a sidewall and a bottom. A first barrier metal layer is disposed on the sidewall of the via hole, but not on the bottom of the via hole. A metal under-layer is formed on the bottom of the via hole and on the first barrier metal layer. A second barrier metal layer is formed on the metal under-layer. A metal fill layer fills the via hole. A lattice mismatch between the metal under-layer and the second barrier metal layer is less than about 5%.
摘要翻译：通过半导体产品互连的结构和工艺流程。提供底部金属层以表示半导体产品中的连接层。底部金属层上的隔离层包括露出底部金属层的一部分的通孔。通孔包括侧壁和底部。第一阻挡金属层设置在通孔的侧壁上，但不设置在通孔的底部。在通孔的底部和第一阻挡金属层上形成金属底层。在金属底层上形成第二阻挡金属层。金属填充层填充通孔。金属底层和第二阻挡金属层之间的晶格失配小于约5％。

4. 发明申请

US20070252277A1 SEMICONDUCTOR DEVICES AND FABRICATION METHOD THEREOF 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070252277A1
公开(公告)日：2007-11-01
申请号：US11380666
申请日：2006-04-28
申请人： Jung-Chih Tsao , Kei-Wei Chen , Shih-Chieh Chang , Yu-Ku Lin , Ying-Lang Wang
发明人： Jung-Chih Tsao , Kei-Wei Chen , Shih-Chieh Chang , Yu-Ku Lin , Ying-Lang Wang
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L23/485 , H01L21/76844 , H01L21/76865 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device. The semiconductor device includes a substrate, a dielectric layer formed thereon, an opening formed in the dielectric layer, a first barrier layer overlying the sidewall of the opening, a second barrier layer overlying the first barrier layer and the bottom of the opening, and a conductive layer filled into the opening. The invention also provides a method of fabricating the semiconductor device.
摘要翻译：半导体器件。所述半导体器件包括：衬底，形成在其上的电介质层，形成在所述电介质层中的开口;覆盖所述开口侧壁的第一阻挡层，覆盖所述第一阻挡层和所述开口底部的第二势垒层;以及导电层填充入开口。本发明还提供一种制造半导体器件的方法。

5. 发明授权

US07071100B2 Method of forming barrier layer with reduced resistivity and improved reliability in copper damascene process 失效
标题翻译：在铜镶嵌工艺中形成具有降低电阻率和改善可靠性的阻挡层的方法
公开(公告)号：US07071100B2
公开(公告)日：2006-07-04
申请号：US10788912
申请日：2004-02-27
申请人： Kei-Wei Chen , Jung-Chih Tsao , Chi-Wen Liu , Jchung-Chang Chen , Shih-Tzung Chang , Shih-Ho Lin , Yu-Ku Lin , Ying-Lang Wang
发明人： Kei-Wei Chen , Jung-Chih Tsao , Chi-Wen Liu , Jchung-Chang Chen , Shih-Tzung Chang , Shih-Ho Lin , Yu-Ku Lin , Ying-Lang Wang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76844 , H01L21/76807 , H01L21/76862 , H01L21/76865
摘要： A method for forming a copper dual damascene with improved copper migration resistance and improved electrical resistivity including providing a semiconductor wafer including upper and lower dielectric insulating layers separated by a middle etch stop layer; forming a dual damascene opening extending through a thickness of the upper and lower dielectric insulating layers wherein an upper trench line portion extends through the upper dielectric insulating layer thickness and partially through the middle etch stop layer; blanket depositing a barrier layer including at least one of a refractory metal and refractory metal nitride to line the dual damascene opening; carrying out a remote plasma etch treatment of the dual damascene opening to remove a bottom portion of the barrier layer to reveal an underlying conductive area; and, filling the dual damascene opening with copper to provide a substantially planar surface.
摘要翻译：一种用于形成具有改善的铜迁移阻力和改善的电阻率的铜双镶嵌的方法，包括提供包括由中间蚀刻停止层分隔的上和下介电绝缘层的半导体晶片; 形成延伸通过上下介电绝缘层的厚度的双镶嵌开口，其中上沟槽线部分延伸穿过上介电绝缘层的厚度并部分地穿过中蚀刻停止层; 毯子沉积包括难熔金属和难熔金属氮化物中的至少一种的阻挡层，以便排列双镶嵌开口; 对双镶嵌开口执行远程等离子体蚀刻处理以去除阻挡层的底部以露出下面的导电区域; 并且用铜填充双镶嵌开口以提供基本平坦的表面。

6. 发明申请

US20050191855A1 Method of forming barrier layer with reduced resistivity and improved reliability in copper damascene process 失效
标题翻译：在铜镶嵌工艺中形成具有降低电阻率和改善可靠性的阻挡层的方法
公开(公告)号：US20050191855A1
公开(公告)日：2005-09-01
申请号：US10788912
申请日：2004-02-27
申请人： Kei-Wei Chen , Jung-Chih Tsao , Chi-Wen Liu , Jchung-Chang Chen , Shih-Tzung Chang , Shih-Ho Lin , Yu-Ku Lin , Ying-Lang Wang
发明人： Kei-Wei Chen , Jung-Chih Tsao , Chi-Wen Liu , Jchung-Chang Chen , Shih-Tzung Chang , Shih-Ho Lin , Yu-Ku Lin , Ying-Lang Wang
IPC分类号： H01L21/44 , H01L21/768
CPC分类号： H01L21/76844 , H01L21/76807 , H01L21/76862 , H01L21/76865
摘要： A method for forming a copper dual damascene with improved copper migration resistance and improved electrical resistivity including providing a semiconductor wafer including upper and lower dielectric insulating layers separated by a middle etch stop layer; forming a dual damascene opening extending through a thickness of the upper and lower dielectric insulating layers wherein an upper trench line portion extends through the upper dielectric insulating layer thickness and partially through the middle etch stop layer; blanket depositing a barrier layer including at least one of a refractory metal and refractory metal nitride to line the dual damascene opening; carrying out a remote plasma etch treatment of the dual damascene opening to remove a bottom portion of the barrier layer to reveal an underlying conductive area; and, filling the dual damascene opening with copper to provide a substantially planar surface.
摘要翻译：一种用于形成具有改善的铜迁移阻力和改善的电阻率的铜双镶嵌的方法，包括提供包括由中间蚀刻停止层分隔的上和下介电绝缘层的半导体晶片; 形成延伸通过上下介电绝缘层的厚度的双镶嵌开口，其中上沟槽线部分延伸穿过上介电绝缘层的厚度并部分地穿过中蚀刻停止层; 毯子沉积包括难熔金属和难熔金属氮化物中的至少一种的阻挡层，以便排列双镶嵌开口; 对双镶嵌开口执行远程等离子体蚀刻处理以去除阻挡层的底部以露出下面的导电区域; 并且用铜填充双镶嵌开口以提供基本平坦的表面。

7. 发明申请

US20070152342A1 Via structure and process for forming the same 有权
标题翻译：通过结构及其形成方法
公开(公告)号：US20070152342A1
公开(公告)日：2007-07-05
申请号：US11323484
申请日：2005-12-30
申请人： Jung-Chih Tsao , Kei-Wei Chen , Ying-Jing Lu , Yu-Sheng Wang , Yu-Ku Lin
发明人： Jung-Chih Tsao , Kei-Wei Chen , Ying-Jing Lu , Yu-Sheng Wang , Yu-Ku Lin
IPC分类号： H01L23/52
CPC分类号： H01L21/76844 , H01L21/76805 , H01L21/76846 , H01L21/76865 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Via structure and process flow for interconnection in a semiconductor product. A bottom metal layer is provided to represent a connection layer in the semiconductor product. An isolation layer on the bottom metal layer comprises a via hole exposing a portion of the bottom metal layer. The via hole comprises a sidewall and a bottom. A first barrier metal layer is disposed on the sidewall of the via hole, but not on the bottom of the via hole. A metal under-layer is formed on the bottom of the via hole and on the first barrier metal layer. A second barrier metal layer is formed on the metal under-layer. A metal fill layer fills the via hole. A lattice mismatch between the metal under-layer and the second barrier metal layer is less than about 5%.
摘要翻译：通过半导体产品互连的结构和工艺流程。提供底部金属层以表示半导体产品中的连接层。底部金属层上的隔离层包括露出底部金属层的一部分的通孔。通孔包括侧壁和底部。第一阻挡金属层设置在通孔的侧壁上，但不设置在通孔的底部。在通孔的底部和第一阻挡金属层上形成金属底层。在金属底层上形成第二阻挡金属层。金属填充层填充通孔。金属底层和第二阻挡金属层之间的晶格失配小于约5％。

8. 发明申请

US20070126120A1 Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20070126120A1
公开(公告)日：2007-06-07
申请号：US11294789
申请日：2005-12-06
申请人： Jung-Chih Tsao , Kei-Wei Chen , Yu-Ku Lin
发明人： Jung-Chih Tsao , Kei-Wei Chen , Yu-Ku Lin
IPC分类号： H01L23/52 , H01L23/48 , H01L29/40
CPC分类号： H01L23/5226 , H01L21/76805 , H01L21/76807 , H01L21/76832 , H01L21/76844 , H01L21/76846 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： Semiconductor devices and methods for fabricating the same. An exemplary device includes a substrate, a dielectric layer, a protection layer, and a conformal barrier layer. The dielectric layer overlies the substrate and comprises an opening. The opening comprises a lower portion and a wider upper portion, exposing parts of the substrate. The bottoms of the upper portion act as shoulders of the opening. The protection layer overlies at least one shoulder of the opening. The conformal barrier layer is disposed in the opening and overlies the protection layer and the dielectric layer, wherein etching resistance of the protection layer against inert-gas plasma is higher than that of the barrier layer.
摘要翻译：半导体器件及其制造方法。示例性器件包括衬底，电介质层，保护层和共形阻挡层。电介质层覆盖在衬底上并且包括开口。开口包括下部和较宽的上部，暴露基底的部分。上部的底部作为开口的肩部。保护层覆盖开口的至少一个肩部。共形阻挡层设置在开口中并覆盖保护层和电介质层，其中保护层对惰性气体等离子体的耐蚀性高于阻挡层的抗蚀性。

9. 发明申请

US20070034517A1 Interconnect structure for semiconductor devices 有权
标题翻译：半导体器件的互连结构
公开(公告)号：US20070034517A1
公开(公告)日：2007-02-15
申请号：US11197009
申请日：2005-08-04
申请人： Jung-Chih Tsao , Kei-Wei Chen , Yu-Ku Lin , Chyi Chern
发明人： Jung-Chih Tsao , Kei-Wei Chen , Yu-Ku Lin , Chyi Chern
IPC分类号： B05D5/12 , C25D5/02
CPC分类号： C25D5/10 , C25D5/18 , C25D7/123 , H01L21/2885 , H01L21/76847 , H01L21/76877
摘要： An interconnect structure for a semiconductor device and its method of manufacture is described. The interconnect structure comprises a multi-layer structure having one or more stress-relief layers. In an embodiment, stress-relief layers are positioned between layers of electroplated copper or other conductive material. The stress-relief layer counteracts stress induced by the conductive material and helps prevent or reduce a pull-back void. For an interconnect structure using electroplated copper, the stress-relief layer may be formed by temporarily reducing the electroplating current, thereby causing a thin film of copper having a larger grain size to be formed between other layers of copper. The larger grain size typically exhibits more of a compressive stress than copper with a smaller grain size. The stress relief layer may also be formed of other materials, such as SIP-Cu, Ta, SiC, or the like.
摘要翻译：描述了半导体器件的互连结构及其制造方法。互连结构包括具有一个或多个应力消除层的多层结构。在一个实施例中，应力消除层位于电镀铜或其它导电材料的层之间。应力消除层抵消由导电材料引起的应力，并有助于防止或减少拉回空隙。对于使用电镀铜的互连结构，可以通过暂时减少电镀电流来形成应力消除层，从而在其它铜层之间形成具有较大晶粒尺寸的铜的薄膜。较大的晶粒尺寸通常表现出比具有较小晶粒尺寸的铜更多的压缩应力。应力消除层也可以由其它材料形成，例如SIP-Cu，Ta，SiC等。

10. 发明授权

US07208404B2 Method to reduce Rs pattern dependence effect 有权
标题翻译：减少Rs模式依赖效应的方法
公开(公告)号：US07208404B2
公开(公告)日：2007-04-24
申请号：US10687183
申请日：2003-10-16
申请人： Jung-Chih Tsao , Chi-Wen Li , Kei-Wei Chen , Jye-Wei Hsu , Hsien-Pin Fong , Steven Lin , Ray Chuang
发明人： Jung-Chih Tsao , Chi-Wen Li , Kei-Wei Chen , Jye-Wei Hsu , Hsien-Pin Fong , Steven Lin , Ray Chuang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76877 , H01L21/288 , H01L21/7684
摘要： A method of forming a copper interconnect in an opening within a pattern is described. The copper interconnect has an Rs that is nearly independent of opening width and pattern density. A first copper layer having a concave upper surface and thickness t1 is formed in a via or trench in a dielectric layer by depositing copper and performing a first CMP step. A second copper layer with a thickness t2 where t2≦t1 and having a convex lower surface is deposited on the first copper layer by a selective electroplating method. The first and second copper layers are annealed and then a second CMP step planarizes the second copper layer to become coplanar with the dielectric layer. The invention is also a copper interconnect comprised of the aforementioned copper layers where the first copper layer has a grain density (GD1)≧GD2 for the second copper layer.
摘要翻译：描述了在图案内的开口中形成铜互连的方法。铜互连具有几乎独立于开口宽度和图案密度的Rs。通过沉积铜并执行第一CMP步骤，在电介质层中的通孔或沟槽中形成具有凹上表面和厚度t 1的第一铜层。具有厚度为2 的第二铜层，其中具有凸下表面的第二铜层沉积在第一铜层上通过选择性电镀方法。对第一和第二铜层进行退火，然后第二CMP步骤将第二铜层平坦化成与电介质层共面。本发明也是由上述铜层构成的铜布线，其中第一铜层具有第二铜层的晶粒密度（G SUB D1）= G D2 D2。

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