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1. 发明授权

US06446242B1 Method and apparatus for storing a validation number in a field-programmable gate array 有权
标题翻译：用于在现场可编程门阵列中存储验证号码的方法和装置
公开(公告)号：US06446242B1
公开(公告)日：2002-09-03
申请号：US09285563
申请日：1999-04-02
申请人： Jung-Cheun Lien , Sheng Feng , Chung-yuan Sun , Eddy Chieh Huang
发明人： Jung-Cheun Lien , Sheng Feng , Chung-yuan Sun , Eddy Chieh Huang
IPC分类号： G06F1750
CPC分类号： G06F21/121 , G06F17/5054
摘要： An apparatus including a field-programmable gate array (FPGA) where the FPGA includes a plurality of X signal lines, a plurality of Y signal lines, and a plurality of memory cells. A first set of the memory cells are used to implement programmable interconnections between the X and Y signal lines and logic functions such as are implemented by configurable functional blocks, and a second set of the memory cells are not used to implement programmable interconnections between the X and Y signal lines or logic functions. Configuration data that is used to implement a specific configuration of the programmable interconnections between the X and Y signal lines and the logic function is stored in the first set of memory cells, and at least a portion of a validation number is stored in at least some of the second set of memory cells. A method of configuring an FPGA includes storing configuration data used for configuring programmable interconnections among a plurality of X and Y signal lines and other logic functions in memory cells in the FPGA used for implementing the programmable interconnections and logic functions, and storing bits of data that form at least a portion of a validation number in memory cells in the FPGA that are not used for implementing the programmable interconnections or logic functions.
摘要翻译：一种包括现场可编程门阵列（FPGA）的装置，其中FPGA包括多条X信号线，多条Y信号线和多个存储单元。第一组存储器单元用于实现X和Y信号线之间的可编程互连以及诸如由可配置功能块实现的逻辑功能，并且第二组存储器单元不用于实现X之间的可编程互连和Y信号线或逻辑功能。用于实现X和Y信号线之间的可编程互连的特定配置和逻辑功能的配置数据被存储在第一组存储器单元中，并且验证号码的至少一部分被存储在至少一些的第二组存储单元。配置FPGA的方法包括存储用于在多个X和Y信号线之间配置可编程互连的配置数据以及用于实现可编程互连和逻辑功能的FPGA中的存储器单元中的其他逻辑功能，以及存储数据位形成FPGA中不用于实现可编程互连或逻辑功能的存储器单元中的验证号码的至少一部分。

2. 发明授权

US06504398B1 Integrated circuit that includes a field-programmable gate array and a hard gate array having the same underlying structure 失效
标题翻译：集成电路包括现场可编程门阵列和具有相同底层结构的硬门阵列
公开(公告)号：US06504398B1
公开(公告)日：2003-01-07
申请号：US09688454
申请日：2000-10-16
申请人： Jung-Cheun Lien , Sheng Feng , Chung-yuan Sun , Eddy Chieh Huang
发明人： Jung-Cheun Lien , Sheng Feng , Chung-yuan Sun , Eddy Chieh Huang
IPC分类号： H03K738
CPC分类号： H03K19/1735 , H03K7/04 , H03K19/17732 , H03K19/17796
摘要： An integrated circuit (IC) includes both a field-programmable gate array (FPGA) and a hard array (HA). The FPGA includes a first set of functional groups that each include an underlying logic structure and memory cells for programming the underlying logic structure, a first set of routing buses, and a first set of routing interconnect areas that provide interconnections between the first set of functional groups and the first set of routing buses. The first set of routing interconnect areas includes transistors and memory cells for programming the interconnections. The HA includes a second set of functional groups that is equal in number to the first set of functional groups and that are arranged like the first set of functional groups. Each functional group in the second set of functional groups includes an underlying logic structure that is like the underlying logic structure of the first set of functional groups but which does not include memory cells for programming the underlying logic structure. The HA also includes a second set of routing buses that are arranged like the first set of routing buses and a second set of routing interconnect areas that are arranged like the first set of routing interconnect areas but which do not include transistors and memory cells for programming interconnections.
摘要翻译：集成电路（IC）包括现场可编程门阵列（FPGA）和硬阵列（HA）。 FPGA包括第一组功能组，每组包括底层逻辑结构和用于编程底层逻辑结构的存储单元，第一组路由总线，以及第一组路由互连区域，其提供第一组功能之间的互连组和第一组路由总线。第一组路由互连区域包括用于对互连进行编程的晶体管和存储单元。 HA包括第二组功能组，其数量与第一组功能组相同，并且排列成与第一组功能组相同。第二组功能组中的每个功能组包括底层逻辑结构，其类似于第一组功能组的底层逻辑结构，但不包括用于编程底层逻辑结构的存储单元。 HA还包括第二组路由总线，其布置为类似于第一组路由总线，以及第二组路由互连区域，其布置为类似于第一组路由互连区域，但不包括用于编程的晶体管和存储器单元互连。

3. 发明授权

US06301696B1 Final design method of a programmable logic device that is based on an initial design that consists of a partial underlying physical template 失效
标题翻译：基于由部分底层物理模板组成的初始设计的可编程逻辑器件的最终设计方法
公开(公告)号：US06301696B1
公开(公告)日：2001-10-09
申请号：US09281008
申请日：1999-03-30
申请人： Jung-Cheun Lien , Eddy Chieh Huang , Chung-yuan Sun , Sheng Feng
发明人： Jung-Cheun Lien , Eddy Chieh Huang , Chung-yuan Sun , Sheng Feng
IPC分类号： G06F1750
CPC分类号： G06F17/5045 , H01L27/11803
摘要： A method of making an integrated circuit (IC) includes establishing an initial design for a field-programmable gate array (FPGA) to be included in the IC that includes programmable connections that can be programmed to implement a desired function; establishing an underlying physical template for the IC wherein at least a portion of the template is based on the initial design for the FPGA; selecting a specific configuration of the programmable connections in the FPGA; performing a manufacturing process of the IC using the underlying physical template, and, during the manufacturing process of the IC, bypassing selected on-state transistors in the FPGA used to implement the specific configuration of the programmable connections with metal connections while conserving the underlying physical template. An IC includes a semiconductor substrate and an FPGA fabricated on the semiconductor substrate. The FPGA has a final design that is based on an initial design contemplated by at least a portion of an underlying physical template used for making the IC. The initial design includes programmable connections that can be programmed to implement a desired function and the final design implements a specific configuration of the programmable connections of the initial design. The FPGA includes a plurality of transistors configured to implement the programmable connections of the initial design, and metal connections configured to bypass selected ones of the plurality of transistors as part of implementing the final design.
摘要翻译：一种制造集成电路（IC）的方法包括建立要包括在IC中的现场可编程门阵列（FPGA）的初始设计，其包括可编程以实现期望功能的可编程连接; 建立IC的基础物理模板，其中模板的至少一部分基于FPGA的初始设计; 选择FPGA中可编程连接的具体配置; 使用下面的物理模板执行IC的制造过程，并且在IC的制造过程期间，旁路用于FPGA中的选定的状态晶体管，用于实现具有金属连接的可编程连接的特定配置，同时节省基础物理模板。 IC包括半导体衬底和在半导体衬底上制造的FPGA。 FPGA具有基于由用于制造IC的底层物理模板的至少一部分所考虑的初始设计的最终设计。初始设计包括可编程以实现所需功能的可编程连接，最终设计实现初始设计的可编程连接的特定配置。 FPGA包括配置成实现初始设计的可编程连接的多个晶体管，以及被配置为绕过多个晶体管中的选定晶体管的金属连接器，作为实现最终设计的一部分。

4. 发明授权

US06211697B1 Integrated circuit that includes a field-programmable gate array and a hard gate array having the same underlying structure 有权
标题翻译：集成电路包括现场可编程门阵列和具有相同底层结构的硬门阵列
公开(公告)号：US06211697B1
公开(公告)日：2001-04-03
申请号：US09318198
申请日：1999-05-25
申请人： Jung-Cheun Lien , Sheng Feng , Chung-yuan Sun , Eddy Chieh Huang
发明人： Jung-Cheun Lien , Sheng Feng , Chung-yuan Sun , Eddy Chieh Huang
IPC分类号： H03K738
CPC分类号： H03K19/1735 , H03K7/04 , H03K19/17732 , H03K19/17796
摘要： An integrated circuit (IC) includes both a field-programmable gate array (FPGA) and a hard array (HA). The FPGA includes a first set of functional groups that each include an underlying logic structure and memory cells for programming the underlying logic structure, a first set of routing buses, and a first set of routing interconnect areas that provide interconnections between the first set of functional groups and the first set of routing buses. The first set of routing interconnect areas includes transistors and memory cells for programming the interconnections. The HA includes a second set of functional groups that is equal in number to the first set of functional groups and that are arranged like the first set of functional groups. Each functional group in the second set of functional groups includes an underlying logic structure that is like the underlying logic structure of the first set of functional groups but which does not include memory cells for programming the underlying logic structure. The HA also includes a second set of routing buses that are arranged like the first set of routing buses and a second set of routing interconnect areas that are arranged like the first set of routing interconnect areas but which do not include transistors and memory cells for programming interconnections.
摘要翻译：集成电路（IC）包括现场可编程门阵列（FPGA）和硬阵列（HA）。 FPGA包括第一组功能组，每组包括底层逻辑结构和用于编程底层逻辑结构的存储单元，第一组路由总线，以及第一组路由互连区域，其提供第一组功能之间的互连组和第一组路由总线。第一组路由互连区域包括用于对互连进行编程的晶体管和存储单元。 HA包括第二组功能组，其数量与第一组功能组相同，并且排列成与第一组功能组相同。第二组功能组中的每个功能组包括底层逻辑结构，其类似于第一组功能组的底层逻辑结构，但不包括用于编程底层逻辑结构的存储单元。 HA还包括第二组路由总线，其布置为类似于第一组路由总线，以及第二组路由互连区域，其布置为类似于第一组路由互连区域，但不包括用于编程的晶体管和存储器单元互连。

5. 发明授权

US07137095B1 Freeway routing system for a gate array 失效
标题翻译：高速公路路由系统为门阵列
公开(公告)号：US07137095B1
公开(公告)日：2006-11-14
申请号：US10077189
申请日：2002-02-15
申请人： Tong Liu , Jung-Cheun Lien , Sheng Feng , Eddy C. Huang , Chung-Yuan Sun , Naihui Liao , Weidong Xiong
发明人： Tong Liu , Jung-Cheun Lien , Sheng Feng , Eddy C. Huang , Chung-Yuan Sun , Naihui Liao , Weidong Xiong
IPC分类号： G06F17/50 , H03K19/177
CPC分类号： G06F17/5054 , G06F17/5077 , H03K19/17732 , H03K19/17736 , H03K19/17796
摘要： A freeway routing system that connects interface groups in said field programmable gate array. The freeway system has a first set of routing conductors configured to transfer signals to the input ports of at least one interface group in a first tile of the field programmable gate array and configured to transfer signals from the output ports of other tiles in the field programmable gate array. The first set of conductors include vertical conductors that form intersections horizontal conductors and programmable interconnect elements located at the intersections of the vertical conductors and horizontal conductors in a diagonal orientation to connect each of horizontal conductors to one of the vertical conductors.
摘要翻译：连接所述现场可编程门阵列中的接口组的高速路由系统。高速公路系统具有第一组路由导体，其被配置为将信号传送到现场可编程门阵列的第一瓦片中的至少一个接口组的输入端口，并且被配置为从现场可编程的其它瓦片的输出端口传送信号门阵列第一组导体包括垂直导体，其形成交叉点水平导体和位于垂直导体和水平导体的交叉点处的对准方向的可编程互连元件，以将每个水平导体连接到垂直导体之一。

6. 发明授权

US06968487B1 User available body scan chain 有权
标题翻译：用户可用的身体扫描链
公开(公告)号：US06968487B1
公开(公告)日：2005-11-22
申请号：US10071262
申请日：2002-02-07
申请人： Ian Bryant , Chung-Yuan Sun , Sheng Feng , Jung-Cheun Lien , Stephen Chan
发明人： Ian Bryant , Chung-Yuan Sun , Sheng Feng , Jung-Cheun Lien , Stephen Chan
IPC分类号： H03K19/177 , G01R31/28 , G06G7/48 , H03K17/693
CPC分类号： G06F17/5054 , G06F17/5077 , H03K19/17732 , H03K19/17736 , H03K19/17796
摘要： A method of accessing the testing means in a Field Programmable Gate Array (“FPGA”) comprised of a plurality of functional groups (“FGs”) comprising: inputting a function netlist defining a user circuit; compiling said function netlist; and generating a logic Built-In Self Test (“BIST”) netlist; wherein said BIST netlist replaces all user registers with scan registers with a scan chain routed as the physical silicon scan chains.
摘要翻译：一种在由多个功能组（“FG”）组成的现场可编程门阵列（“FPGA”）中访问测试装置的方法，包括：输入定义用户电路的功能网表; 编译功能网表; 并生成逻辑内置自检（“BIST”）网表; 其中所述BIST网表用扫描链替换具有扫描寄存器的所有用户寄存器，所述扫描链作为物理硅扫描链路由。

7. 发明授权

US06700404B1 Tileable field-programmable gate array architecture 有权
标题翻译：可拼接现场可编程门阵列架构
公开(公告)号：US06700404B1
公开(公告)日：2004-03-02
申请号：US10066398
申请日：2002-01-30
申请人： Sheng Feng , Jung-Cheun Lien , Eddy C. Huang , Chung-Yuan Sun , Tong Liu , Naihui Liao , Weidong Xiong
发明人： Sheng Feng , Jung-Cheun Lien , Eddy C. Huang , Chung-Yuan Sun , Tong Liu , Naihui Liao , Weidong Xiong
IPC分类号： H03K19177
CPC分类号： G06F17/5054 , G06F17/5077 , H03K19/17732 , H03K19/17736 , H03K19/17796
摘要： An apparatus includes a field-programmable gate array (FPGA). The FPGA includes a first FPGA tile, and the first FPGA tile includes a plurality of functional groups (FGs), a third set of routing conductors, in addition to a first set of routing conductors and a second set of routing conductors and a plurality of interface groups (IGs). The plurality of FGs are arranged in rows and columns with each of the FGs being configured to receive tertiary input signals as well as regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the first FPGA tile, and provide input signals to the third set of input ports of the FGs. The plurality of IGs surround the plurality of FGs such that one IG is positioned at each end of each row and column. Each of the IGs is coupled to the third set of routing conductors and configured to transfer signals from the third set of routing conductors to outside of the first FPGA tile.
摘要翻译：一种装置包括现场可编程门阵列（FPGA）。所述FPGA包括第一FPGA瓦片，并且所述第一FPGA瓦片除了第一组路由导体和第二组布线导体以及多个布线导体之外，还包括多个功能组（FG），第三组布线导体接口组（IG）。多个FG布置成行和列，其中每个FG被配置为接收三次输入信号以及常规输入信号，执行逻辑运算并产生常规输出信号。第三组路由导体被耦合到FG的第一组输出端口并且被配置为接收信号，在第一FPGA瓦片内路由信号，并且向FG的第三组输入端口提供输入信号。多个IG围绕多个FG，使得一个IG位于每行和每列的每一端。每个IG耦合到第三组路由导体并且被配置为将信号从第三组路由导体传送到第一FPGA片外部。

8. 发明授权

US06611153B1 Tileable field-programmable gate array architecture 失效
公开(公告)号：US06611153B1
公开(公告)日：2003-08-26
申请号：US10061955
申请日：2002-01-31
申请人： Jung-Cheun Lien , Sheng Feng , Eddy C. Huang , Chung-Yuan Sun , Tong Liu , Naihui Liao
发明人： Jung-Cheun Lien , Sheng Feng , Eddy C. Huang , Chung-Yuan Sun , Tong Liu , Naihui Liao
IPC分类号： H03K19177
CPC分类号： G06F17/5054 , G06F17/5077 , H03K19/17732 , H03K19/17736 , H03K19/17796
摘要： An apparatus includes a field-programmable gate array (FPGA). The FPGA includes a first FPGA tile, and the first FPGA tile includes a plurality of functional groups (FGs), a regular routing structure, and a plurality of interface groups (IGs). The plurality of FGs are arranged in rows and columns with each of the FGs being configured to receive regular input signals, perform a logic operation, and generate regular output signals. The regular routing structure is coupled to the FGs and configured to receive the regular output signals, route signals within the first FPGA tile, and provide the regular input signals to the FGs. The routability of the regular routing structure is maximized by depositing switches according to designators. This novel designation method provides the same routability with approximately half the switches. Thus, further reduction in routing area is achieved. The plurality of IGs surround the plurality of FGs such that one IG is positioned at each end of each row and column. Each of the IGs is coupled to the regular routing structure and configured to transfer signals from the regular routing structure to outside of the first FPGA tile.

9. 发明授权

US06870396B2 Tileable field-programmable gate array architecture 有权
标题翻译：可拼接现场可编程门阵列架构
公开(公告)号：US06870396B2
公开(公告)日：2005-03-22
申请号：US10429004
申请日：2003-04-30
申请人： Jung-Cheun Lien , Sheng Feng , Eddy C. Huang , Chung-Yuan Sun , Tong Liu , Naihui Liao
发明人： Jung-Cheun Lien , Sheng Feng , Eddy C. Huang , Chung-Yuan Sun , Tong Liu , Naihui Liao
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/17732
摘要： An apparatus includes a field-programmable gate array (FPGA). The FPGA includes a first FPGA tile, and the first FPGA tile includes a plurality of functional groups (FGs), a regular routing structure, and a plurality of interface groups (IGs). The plurality of FGs are arranged in rows and columns with each of the FGs being configured to receive regular input signals, perform a logic operation, and generate regular output signals. The regular routing structure is coupled to the FGs and configured to receive the regular output signals, route signals within the first FPGA tile, and provide the regular input signals to the FGs. The routability of the regular routing structure is maximized by depositing switches according to designators. This novel designation method provides the same routability with approximately half the switches. Thus, further reduction in routing area is achieved. The plurality of IGs surround the plurality of FGs such that one IG is positioned at each end of each row and column. Each of the IGs is coupled to the regular routing structure and configured to transfer signals from the regular routing structure to outside of the first FPGA tile.
摘要翻译：一种装置包括现场可编程门阵列（FPGA）。 FPGA包括第一FPGA片，并且第一FPGA片包括多个功能组（FG），规则路由结构以及多个接口组（IG）。多个FG布置成行和列，其中每个FG被配置为接收常规输入信号，执行逻辑运算并产生规则的输出信号。常规路由结构耦合到FG并被配置成接收常规输出信号，在第一FPGA片内路由信号，并向FG提供常规输入信号。通过根据指示符存放交换机来最大化常规路由结构的可路由性。这种新颖的指定方法与大约一半的开关提供相同的可路由性。因此，实现了路由区域的进一步减少。多个IG围绕多个FG，使得一个IG位于每行和每列的每一端。每个IG耦合到常规路由结构并且被配置为将信号从常规路由结构传送到第一FPGA块的外部。

10. 发明授权

US06744278B1 Tileable field-programmable gate array architecture 有权
公开(公告)号：US06744278B1
公开(公告)日：2004-06-01
申请号：US10061951
申请日：2002-01-31
申请人： Tong Liu , Jung-Cheun Lien , Sheng Feng , Eddy C. Huang , Chung-Yuan Sun , Naihui Liao
发明人： Tong Liu , Jung-Cheun Lien , Sheng Feng , Eddy C. Huang , Chung-Yuan Sun , Naihui Liao
IPC分类号： H03K19177
CPC分类号： G06F17/5054 , G06F17/5077 , H03K19/17732 , H03K19/17736 , H03K19/17796
摘要： An apparatus includes a field-programmable gate array (FPGA). The FPGA includes a first FPGA tile, and the first FPGA tile includes a plurality of functional groups (FGs), a third set of routing conductors, in addition to a first set of routing conductors and a second set of routing conductors and a plurality of interface groups (IGs). The plurality of FGs are arranged in rows and columns with each of the FGs being configured to receive tertiary input signals as well as regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the first FPGA tile, and provide input signals to the third set of input ports of the FGs. The plurality of IGs surround the plurality of FGs such that one IG is positioned at each end of each row and column. Each of the IGs is coupled to the third set of routing conductors and configured to transfer signals from the third set of routing conductors to outside of the first FPGA tile.

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