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    • 5. 发明申请
    • Method for forming polysilicon plug of semiconductor device
    • 用于形成半导体器件的多晶硅插塞的方法
    • US20050142867A1
    • 2005-06-30
    • US10879220
    • 2004-06-30
    • Hyung ParkMin LeeSang LeeHyun Sohn
    • Hyung ParkMin LeeSang LeeHyun Sohn
    • H01L21/28H01L21/3205H01L21/336H01L21/44H01L21/4763H01L21/60H01L21/768
    • H01L21/76897H01L21/7684
    • Disclosed is a method for forming a polysilicon plug of a semiconductor device. The method comprises the steps of: forming a stacked pattern of a wordline and a hard mask film on a semiconductor substrate comprising a cell region and a peripheral circuit region; forming a spacer on a sidewall of the stacked pattern; forming an interlayer insulating film on the semiconductor substrate; polishing the interlayer insulating film via a CMP process using the hard mask film as a polishing barrier film; forming a barrier film on the semiconductor substrate including the interlayer insulating film; selectively etching the barrier film and the interlayer insulating film to form a landing plug contact hole; depositing a polysilicon film filling the landing plug contact hole on the semiconductor substrate; blanket-etching the polysilicon film using the barrier film as an etching barrier film; and polishing the polysilicon film and the barrier film using the hard mask film as a polishing barrier film to form a polysilicon plug.
    • 公开了一种用于形成半导体器件的多晶硅插塞的方法。 该方法包括以下步骤:在包括单元区域和外围电路区域的半导体衬底上形成字线和硬掩模膜的堆叠图案; 在所述堆叠图案的侧壁上形成间隔物; 在半导体衬底上形成层间绝缘膜; 通过使用硬掩模膜作为抛光阻挡膜的CMP工艺来研磨层间绝缘膜; 在包括层间绝缘膜的半导体衬底上形成阻挡膜; 选择性地蚀刻阻挡膜和层间绝缘膜以形成着陆塞接触孔; 在所述半导体衬底上沉积填充所述着地插头接触孔的多晶硅膜; 使用阻挡膜作为蚀刻阻挡膜对多晶硅膜进行绝缘蚀刻; 并使用硬掩模膜作为抛光阻挡膜研磨多晶硅膜和阻挡膜以形成多晶硅插塞。
    • 6. 发明申请
    • Method of manufacturing semiconductor device
    • 制造半导体器件的方法
    • US20050095834A1
    • 2005-05-05
    • US10875052
    • 2004-06-22
    • Sang LeeJong ShinHyung Park
    • Sang LeeJong ShinHyung Park
    • H01L21/283H01L21/304H01L21/44H01L21/4763H01L21/60H01L21/768H01L21/822H01L21/8242
    • H01L21/76897H01L21/7684H01L27/10855H01L27/10873H01L27/10888
    • Disclosed is a method of manufacturing a semiconductor device. The method includes the steps of forming gates on a substrate, forming junction areas on a surface of the substrate, forming a first BPSG layer on a resultant structure of the substrate, performing a first CVD process for the first BPSG layer, forming a second BPSG layer on the first BPSG layer, forming a landing plug contact, depositing a polysilicon layer on a resultant structure of the substrate, and performing a second CMP process for the polysilicon layer, the second BPSG layer and the nitride hard mask. The CMP processes are carried by using acid slurry having a high polishing selectivity with respect to the nitride layer, so a step difference between the cell region and the peripheral region is removed, thereby simplifying the semiconductor manufacturing process and removing a dishing phenomenon.
    • 公开了半导体器件的制造方法。 该方法包括以下步骤:在衬底上形成栅极,在衬底的表面上形成接合区域,在衬底的所得结构上形成第一BPSG层,对第一BPSG层执行第一CVD工艺,形成第二BPSG 在第一BPSG层上形成着色插头接触,在所得衬底的所得结构上沉积多晶硅层,以及对多晶硅层,第二BPSG层和氮化物硬掩模执行第二CMP工艺。 通过使用相对于氮化物层具有高抛光选择性的酸性浆料来进行CMP处理,从而消除了单元区域和外围区域之间的阶跃差异,从而简化了半导体制造工艺并消除了凹陷现象。