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1. 发明申请

US20050090059A1 Method for manufacturing a non-volatile memory device 审中-公开
标题翻译：用于制造非易失性存储器件的方法
公开(公告)号：US20050090059A1
公开(公告)日：2005-04-28
申请号：US10968200
申请日：2004-10-19
申请人： Jung Lee , Seo Chi
发明人： Jung Lee , Seo Chi
IPC分类号： H01L27/10 , H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792 , H01L21/336
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11534 , H01L29/42336
摘要： A method for manufacturing a non-volatile memory device which can increase the coupling ratio and can avoid affecting the height of a control gate by forming a trench in a cell region and forming a floating gate in a concave shape in the trench is disclosed. The method comprises: forming a first trench having a first depth on a silicon substrate of a peripheral circuit region, burying the same with a buried oxide film and planarizing the same; forming a second trench having a second depth on the silicon substrate of the cell region; carrying out channel ion implantation to the cell region, forming a tunnel oxide film in the second trench and depositing a floating gate material; forming a floating gate by etching the floating gate material; forming a source/drain junction in the cell region; forming wells in the peripheral circuit and cell regions and depositing a dielectric film; depositing a gate material while leaving the dielectric film only in the channel portion of the cell region; and forming a gate in the peripheral circuit region and a control gate in the cell region by etching the gate material.
摘要翻译：公开了一种用于制造可以增加耦合比率并且可以避免通过在单元区域中形成沟槽并且在沟槽中形成凹形形状的浮动栅极来影响控制栅极的高度的方法。该方法包括：在外围电路区的硅衬底上形成具有第一深度的第一沟槽，将掩埋氧化膜埋入其中并使其平坦化; 在所述电池区的硅衬底上形成具有第二深度的第二沟槽; 对所述单元区进行沟道离子注入，在所述第二沟槽中形成隧道氧化膜，并沉积浮栅材料; 通过蚀刻浮栅材料形成浮栅; 在所述电池区域中形成源极/漏极结; 在外围电路和电池区中形成阱并沉积介电膜; 沉积栅极材料，同时仅在电池区的沟道部分留下电介质膜; 以及通过蚀刻栅极材料在外围电路区域和单元区域中的控制栅极形成栅极。

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