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1. 发明申请

US20090296458A1 RESISTANCE VARIABLE MEMORY DEVICE AND METHOD OF WRITING DATA 失效
标题翻译：电阻可变存储器件和数据写入方法
公开(公告)号：US20090296458A1
公开(公告)日：2009-12-03
申请号：US12471526
申请日：2009-05-26
申请人： Jung Hyuk Lee , Kwangjin Lee , Daewon Ha , Gitae Jeong , Daehwan Kang
发明人： Jung Hyuk Lee , Kwangjin Lee , Daewon Ha , Gitae Jeong , Daehwan Kang
IPC分类号： G11C11/00
CPC分类号： G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/0064 , G11C13/0069 , G11C2013/0078 , G11C2213/79
摘要： A method of programming a resistance variable memory cell to a given logic state includes applying a first programming current to the memory cell, executing a verify read of the memory cell by sensing a logic state of the memory cell, and applying a second programming current to the memory cell when the sensed logic state is different than the given logic state, where the second programming current is greater than the first programming current
摘要翻译：将电阻变量存储单元编程为给定逻辑状态的方法包括：将第一编程电流施加到存储单元，通过感测存储单元的逻辑状态执行存储单元的校验读取，并将第二编程电流施加到当感测到的逻辑状态不同于给定的逻辑状态时，存储单元，其中第二编程电流大于第一编程电流

2. 发明授权

US08014190B2 Resistance variable memory device and method of writing data 有权
公开(公告)号：US08014190B2
公开(公告)日：2011-09-06
申请号：US13023759
申请日：2011-02-09
申请人： Jung Hyuk Lee , Kwangjin Lee , Daewon Ha , Gitae Jeong , Daehwan Kang
发明人： Jung Hyuk Lee , Kwangjin Lee , Daewon Ha , Gitae Jeong , Daehwan Kang
IPC分类号： G11C11/00
CPC分类号： G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/0064 , G11C13/0069 , G11C2013/0078 , G11C2213/79
摘要： A method of programming a resistance variable memory cell to a given logic state includes applying a first programming current to the memory cell, executing a verify read of the memory cell by sensing a logic state of the memory cell, and applying a second programming current to the memory cell when the sensed logic state is different than the given logic state, where the second programming current is greater than the first programming current.

3. 发明授权

US07907437B2 Resistance variable memory device and method of writing data 失效
标题翻译：电阻变量存储器件及数据写入方法
公开(公告)号：US07907437B2
公开(公告)日：2011-03-15
申请号：US12471526
申请日：2009-05-26
申请人： Jung Hyuk Lee , Kwangjin Lee , Daewon Ha , Gitae Jeong , Daehwan Kang
发明人： Jung Hyuk Lee , Kwangjin Lee , Daewon Ha , Gitae Jeong , Daehwan Kang
IPC分类号： G11C11/00
CPC分类号： G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/0064 , G11C13/0069 , G11C2013/0078 , G11C2213/79
摘要： A method of programming a resistance variable memory cell to a given logic state includes applying a first programming current to the memory cell, executing a verify read of the memory cell by sensing a logic state of the memory cell, and applying a second programming current to the memory cell when the sensed logic state is different than the given logic state, where the second programming current is greater than the first programming current.
摘要翻译：将电阻变量存储单元编程为给定逻辑状态的方法包括：将第一编程电流施加到存储单元，通过感测存储单元的逻辑状态执行存储单元的校验读取，并将第二编程电流施加到当感测到的逻辑状态不同于给定的逻辑状态时，存储单元，其中第二编程电流大于第一编程电流。

4. 发明申请

US20130051123A1 RESISTANCE CHANGE MEMORY DEVICE AND CURRENT TRIMMING METHOD THEREOF 有权
标题翻译：电阻变化存储器件及其电流校准方法
公开(公告)号：US20130051123A1
公开(公告)日：2013-02-28
申请号：US13554146
申请日：2012-07-20
申请人： Jung Hyuk LEE , Daewon Ha , Kyu-Rie Sim
发明人： Jung Hyuk LEE , Daewon Ha , Kyu-Rie Sim
IPC分类号： G11C11/00
CPC分类号： G11C8/00 , G11C11/16 , G11C11/1675 , G11C13/00 , G11C13/0004 , G11C13/0007 , G11C13/0038 , G11C13/0069 , G11C17/16 , G11C29/021 , G11C29/028 , G11C2013/0076 , G11C2013/0083 , G11C2013/0092 , G11C2029/5006
摘要： A resistance change memory device includes an array of resistance change memory cells, and a writing circuit configured to reset a selected memory cell to a high resistance state by supplying a RESET current to the selected memory cell in the array of resistance change memory cells in a program operation mode, wherein a level of the RESET current depends on a distribution of initial RESET currents for the array of resistance change memory cells.
摘要翻译：一种电阻变化存储器件包括一个电阻变化存储单元的阵列，以及一个写入电路，配置成通过向一个电阻变化存储单元阵列中的所选择的存储单元提供RESET电流来将所选择的存储单元复位到高电阻状态程序操作模式，其中RESET电流的电平取决于电阻变化存储单元阵列的初始RESET电流的分布。

5. 发明授权

US08102729B2 Resistive memory device capable of compensating for variations of bit line resistances 有权
标题翻译：能够补偿位线电阻变化的电阻式存储器件
公开(公告)号：US08102729B2
公开(公告)日：2012-01-24
申请号：US12659689
申请日：2010-03-17
申请人： Jung Hyuk Lee , Daewon Ha , Kwang-Woo Lee
发明人： Jung Hyuk Lee , Daewon Ha , Kwang-Woo Lee
IPC分类号： G11C8/08
CPC分类号： G11C13/0004 , G11C8/08 , G11C13/0028 , G11C2213/72
摘要： A variable resistance memory device may include first and second memory cells connected to different lengths of bit lines, respectively, and a select circuit, configured to select the first and second memory cells, which is connected to the first and second memory cells through word lines. The select circuit is configured to compensate for a difference of resistances in the different of the lengths of the bit lines.
摘要翻译：可变电阻存储器件可以包括分别连接到不同长度的位线的第一和第二存储器单元，以及选择电路，其被配置为选择通过字线连接到第一和第二存储器单元的第一和第二存储器单元。选择电路被配置为补偿位线的不同长度中的电阻差。

6. 发明授权

US08830728B2 Resistance change memory device and current trimming method thereof 有权
标题翻译：电阻变化存储器件及其电流修整方法
公开(公告)号：US08830728B2
公开(公告)日：2014-09-09
申请号：US13554146
申请日：2012-07-20
申请人： Jung Hyuk Lee , Daewon Ha , Kyu-Rie Sim
发明人： Jung Hyuk Lee , Daewon Ha , Kyu-Rie Sim
IPC分类号： G11C11/00 , G11C8/00 , G11C29/02 , G11C13/00 , G11C17/16 , G11C11/16 , G11C29/50
CPC分类号： G11C8/00 , G11C11/16 , G11C11/1675 , G11C13/00 , G11C13/0004 , G11C13/0007 , G11C13/0038 , G11C13/0069 , G11C17/16 , G11C29/021 , G11C29/028 , G11C2013/0076 , G11C2013/0083 , G11C2013/0092 , G11C2029/5006
摘要： A resistance change memory device includes an array of resistance change memory cells, and a writing circuit configured to reset a selected memory cell to a high resistance state by supplying a RESET current to the selected memory cell in the array of resistance change memory cells in a program operation mode, wherein a level of the RESET current depends on a distribution of initial RESET currents for the array of resistance change memory cells.
摘要翻译：一种电阻变化存储器件包括一个电阻变化存储单元的阵列，以及一个写入电路，配置成通过向一个电阻变化存储单元阵列中的所选择的存储单元提供RESET电流来将所选择的存储单元复位到高电阻状态程序操作模式，其中RESET电流的电平取决于电阻变化存储单元阵列的初始RESET电流的分布。

7. 发明授权

US08902628B2 Resistive memory device and sensing margin trimming method thereof 有权
标题翻译：电阻式存储器件及其检测边缘微调方法
公开(公告)号：US08902628B2
公开(公告)日：2014-12-02
申请号：US13485163
申请日：2012-05-31
申请人： Daewon Ha , Jung Hyuk Lee
发明人： Daewon Ha , Jung Hyuk Lee
IPC分类号： G11C11/00 , G11C8/10 , G11C13/00
CPC分类号： G11C8/10 , G11C13/0004 , G11C13/0007 , G11C13/003 , G11C13/0038 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2213/75
摘要： A resistive memory device and a sensing margin trimming method are provided. The resistive memory device includes a memory cell array and a trimming circuit. The memory cell array has a plurality of resistive memory cells. The trimming circuit generates a trimming signal according to a characteristic distribution shift value of the resistive memory cells. With the inventive concept, although a characteristic distribution of memory cells is varied, an erroneous read operation is minimized or reduced by securing a sensing margin stably. Accordingly, a fabrication yield of the resistive memory device is bettered.
摘要翻译：提供了一种电阻式存储器件和感测余量修整方法。电阻式存储器件包括存储单元阵列和微调电路。存储单元阵列具有多个电阻存储单元。微调电路根据电阻性存储单元的特征分布偏移值产生微调信号。利用本发明的概念，尽管存储单元的特性分布是变化的，但是通过稳定地确保感测余量来最小化或减少错误的读取操作。因此，提高了电阻式存储器件的制造成品率。

8. 发明申请

US20100271867A1 Variable resistive memory device compensating bit line resistance 有权
标题翻译：可变电阻存储器件补偿位线电阻
公开(公告)号：US20100271867A1
公开(公告)日：2010-10-28
申请号：US12659689
申请日：2010-03-17
申请人： Jung Hyuk Lee , Daewon Ha , Kwang-Woo Lee
发明人： Jung Hyuk Lee , Daewon Ha , Kwang-Woo Lee
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C8/08 , G11C13/0028 , G11C2213/72
摘要： Provided is a variable resistance memory device. The variable resistance memory device may include first and second memory cells connected to different lengths of bit lines, respectively, and a select circuit, configured to select the first and second memory cells, which is connected to the first and second memory cells through word lines. The select circuit is configured to compensate for a difference of resistances in the different of the lengths of the bit lines.
摘要翻译：提供了可变电阻存储器件。可变电阻存储器件可以包括分别连接到不同长度的位线的第一和第二存储器单元，以及选择电路，其被配置为选择通过字线连接到第一和第二存储器单元的第一和第二存储器单元。选择电路被配置为补偿位线的不同长度中的电阻差。

9. 发明授权

US08168479B2 Resistance variable memory device and method of fabricating the same 有权
标题翻译：电阻可变存储器件及其制造方法
公开(公告)号：US08168479B2
公开(公告)日：2012-05-01
申请号：US12717219
申请日：2010-03-04
申请人： Daewon Ha
发明人： Daewon Ha
IPC分类号： H01L21/82
CPC分类号： G11C13/0004 , G11C2213/72 , H01L27/2409 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144
摘要： A method of fabricating a resistance variable device includes forming selection devices on a substrate, forming a conductive layer on the selection devices, patterning the conductive layer in a first direction to form conductive patterns spaced apart from each other in the first direction and connecting a pair of adjacent selection devices to each other in the first direction, forming a resistance-variable-material-layer on the conductive patterns, and patterning the resistance-variable-material-layer and the conductive patterns in a second direction to form rows of resistance-variable material extending in the second direction and to form electrodes spaced apart from one another, such that each electrode corresponds to a separate selection device.
摘要翻译：一种制造电阻可变器件的方法包括在衬底上形成选择器件，在选择器件上形成导电层，在第一方向上形成导电层，以形成在第一方向上彼此间隔的导电图案，并将一对在第一方向上彼此相邻的选择装置，在导电图案上形成电阻可变材料层，并且在第二方向上对电阻变化材料层和导电图案进行图案化以形成电阻 - 可变材料在第二方向上延伸并且形成彼此间隔开的电极，使得每个电极对应于单独的选择装置。

10. 发明授权

US09536968B2 Semiconductor devices including contact patterns having a rising portion and a recessed portion 有权
标题翻译：包括具有上升部分和凹陷部分的接触图案的半导体器件
公开(公告)号：US09536968B2
公开(公告)日：2017-01-03
申请号：US14715643
申请日：2015-05-19
申请人： Sungil Park , Munhyeon Kim , Woonggi Kim , Keunhwi Cho , Hwichan Jun , Dongwon Kim , Daewon Ha
发明人： Sungil Park , Munhyeon Kim , Woonggi Kim , Keunhwi Cho , Hwichan Jun , Dongwon Kim , Daewon Ha
IPC分类号： H01L29/417 , H01L29/45 , H01L29/06 , H01L29/78 , H01L29/66
CPC分类号： H01L29/41775 , H01L29/0653 , H01L29/41791 , H01L29/456 , H01L29/66545 , H01L29/78 , H01L29/785
摘要： Semiconductor devices may include a gate pattern and a contact pattern disposed on an active region. The contact pattern may include a recessed portion near the gate pattern, and a rising portion away from the gate pattern. The gate pattern may include a gate insulating layer and a gate electrode disposed on the gate insulating layer. An upper surface of the recessed portion may be lower than an upper surface of the rising portion.
摘要翻译：半导体器件可以包括设置在有源区上的栅极图案和接触图案。接触图案可以包括靠近栅极图案的凹陷部分和远离栅极图案的上升部分。栅极图案可以包括栅极绝缘层和设置在栅极绝缘层上的栅电极。凹部的上表面可以比上升部的上表面低。

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