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1. 发明授权

US08537677B2 Incremental adaptive packet routing in a multi-dimensional network 有权
标题翻译：在多维网络中增量自适应分组路由
公开(公告)号：US08537677B2
公开(公告)日：2013-09-17
申请号：US12577972
申请日：2009-10-13
申请人： Jung Ho Ahn , Nathan Binkert , Al Davis , Moray McLaren , Robert Schreiber
发明人： Jung Ho Ahn , Nathan Binkert , Al Davis , Moray McLaren , Robert Schreiber
IPC分类号： H04L12/56
CPC分类号： H04L45/125 , H04L45/00 , H04L45/06 , H04L45/22
摘要： Illustrated is a computer system and method that includes a Processing Element (PE) to generate a data packet that is routed along a shortest path that includes a plurality of routers in a multiple dimension network. The system and method further include a router, of the plurality of routers, to de-route the data packet from the shortest path to an additional path, the de-route to occur where the shortest path is congested and the additional path links the router and an additional router in a dimension of the multiple dimension network.
摘要翻译：说明的是包括处理元件（PE）的计算机系统和方法，用于生成沿着包括多维网络中的多个路由器的最短路径路由的数据分组。所述系统和方法还包括所述多个路由器中的路由器将所述数据分组从所述最短路径去路由到附加路径，所述去路由发生在所述最短路径拥塞的地方，并且所述附加路径链接所述路由器以及多维网络维度中的附加路由器。

2. 发明申请

US20110085561A1 Incremental Adaptive Packet Routing In A Multi-Dimensional Network 有权
标题翻译：增量自适应分组路由在多维网络中
公开(公告)号：US20110085561A1
公开(公告)日：2011-04-14
申请号：US12577972
申请日：2009-10-13
申请人： Jung Ho Ahn , Nathan Binkert , Al Davis , Moray McLaren , Robert Schreiber
发明人： Jung Ho Ahn , Nathan Binkert , Al Davis , Moray McLaren , Robert Schreiber
IPC分类号： H04L12/56
CPC分类号： H04L45/125 , H04L45/00 , H04L45/06 , H04L45/22
摘要： Illustrated is a computer system and method that includes a Processing Element (PE) to generate a data packet that is routed along a shortest path that includes a plurality of routers in a multiple dimension network. The system and method further include a router, of the plurality of routers, to de-route the data packet from the shortest path to an additional path, the de-route to occur where the shortest path is congested and the additional path links the router and an additional router in a dimension of the multiple dimension network.
摘要翻译：说明的是包括处理元件（PE）的计算机系统和方法，用于生成沿着包括多维网络中的多个路由器的最短路径路由的数据分组。所述系统和方法还包括所述多个路由器中的路由器将所述数据分组从所述最短路径去路由到附加路径，所述去路由发生在所述最短路径拥塞的地方，并且所述附加路径链接所述路由器以及多维网络维度中的附加路由器。

3. 发明申请

US20090103929A1 Synchronous optical bus providing communication between computer system components 有权
标题翻译：提供计算机系统组件之间的通信的同步光学总线
公开(公告)号：US20090103929A1
公开(公告)日：2009-04-23
申请号：US11977369
申请日：2007-10-23
申请人： Nathan Binkert , Norm Jouppi , Robert Schreiber , Jung Ho Ahn , Moray McLaren
发明人： Nathan Binkert , Norm Jouppi , Robert Schreiber , Jung Ho Ahn , Moray McLaren
IPC分类号： H04B10/00
CPC分类号： H04B10/278 , H04B10/801
摘要： A synchronous optical bus system for communication between computer system components is described. In one example, the optical bus system is used for communication between a memory controller and memory devices optically coupled to an optical interconnect. Optical bus interface units couple the components to the optical interconnect and are arranged on the optical interconnect in order that a sum of an optical path length from a controller component to each computer system component and from each computer system component to the controller component is the same for all the coupled computer system components. A synchronous protocol is used for communication between the components.
摘要翻译：描述了用于计算机系统组件之间的通信的同步光总线系统。在一个示例中，光总线系统用于存储器控制器与光学互连光耦合的存储器件之间的通信。光总线接口单元将组件耦合到光互连，并且布置在光互连上，以便从控制器组件到每个计算机系统组件以及从每个计算机系统组件到控制器组件的光路长度之和相等适用于所有耦合的计算机系统组件。同步协议用于组件之间的通信。

4. 发明授权

US08032033B2 Synchronous optical bus providing communication between computer system components 有权
标题翻译：提供计算机系统组件之间的通信的同步光学总线
公开(公告)号：US08032033B2
公开(公告)日：2011-10-04
申请号：US11977369
申请日：2007-10-23
申请人： Nathan Binkert , Norm Jouppi , Robert Schreiber , Jung Ho Ahn , Moray McLaren
发明人： Nathan Binkert , Norm Jouppi , Robert Schreiber , Jung Ho Ahn , Moray McLaren
IPC分类号： H04B10/20
CPC分类号： H04B10/278 , H04B10/801
摘要： A synchronous optical bus system for communication between computer system components is described. In one example, the optical bus system is used for communication between a memory controller and memory devices optically coupled to an optical interconnect. Optical bus interface units couple the components to the optical interconnect and are arranged on the optical interconnect in order that a sum of an optical path length from a controller component to each computer system component and from each computer system component to the controller component is the same for all the coupled computer system components. A synchronous protocol is used for communication between the components.
摘要翻译：描述了用于计算机系统组件之间的通信的同步光总线系统。在一个示例中，光总线系统用于存储器控制器与光学互连光耦合的存储器件之间的通信。光总线接口单元将组件耦合到光互连，并且布置在光互连上，以便从控制器组件到每个计算机系统组件以及从每个计算机系统组件到控制器组件的光路长度之和相等适用于所有耦合的计算机系统组件。同步协议用于组件之间的通信。

5. 发明授权

US08130754B2 On-chip and chip-to-chip routing using a processor element/router combination 有权
标题翻译：使用处理器元件/路由器组合的片上和芯片到芯片路由
公开(公告)号：US08130754B2
公开(公告)日：2012-03-06
申请号：US12501000
申请日：2009-07-10
申请人： Nathan Binkert , Moray McLaren
发明人： Nathan Binkert , Moray McLaren
IPC分类号： H04L12/50 , H04L12/66
CPC分类号： G06F15/17343 , G06F15/7825
摘要： A system and method is shown for on-chip and chip-to-chip routing. The system and method includes a processor element residing on a processor die to process a data packet received at the processor die. The system and method also include a router residing on the process die to route the data packet received at the processor die. Further, the system and method includes a switch core residing on the processor die to switch a communication channel along which the data packet is to be transmitted. Additionally, the system and method includes a switch core to identify a destination processing element and router (PE/R) module for a data packet, the switch core and the destination PE/R module residing on a common processor die. Moreover, the system and method includes a communication channel to operatively connect the switch core and the destination PE/R module on the common processor die.
摘要翻译：显示了用于片上和芯片到芯片布线的系统和方法。该系统和方法包括驻留在处理器管芯上以处理在处理器管芯处接收的数据包的处理器元件。系统和方法还包括驻留在处理管芯上的路由器来路由在处理器管芯处接收的数据分组。此外，该系统和方法包括位于处理器管芯上的交换机核心，用于切换数据分组将被发送的通信信道。另外，该系统和方法包括一个交换机核心，用于识别驻留在公共处理器管芯上的数据包，交换机核心和目的PE / R模块的目的地处理元件和路由器（PE / R）模块。此外，该系统和方法包括一个通信信道，用于将公共处理器管芯上的交换机核心和目的PE / R模块连接起来。

6. 发明申请

US20130266309A1 SWITCHING IN A NETWORK DEVICE 有权
标题翻译：在网络设备中切换
公开(公告)号：US20130266309A1
公开(公告)日：2013-10-10
申请号：US13696631
申请日：2010-05-20
申请人： Nathan Binkert , Moray McLaren , Michael Tan
发明人： Nathan Binkert , Moray McLaren , Michael Tan
IPC分类号： H04L12/24
CPC分类号： H04L41/0826 , H04L49/253 , H04L49/30 , H04L49/40 , H04Q11/0066 , H04Q11/0071 , H04Q2011/0081
摘要： As described herein, a network device includes an optical circuit switch to perform circuit switching. The network device also has a plurality of removable line cards, each of which includes a packet switch. A switching manager automatically reconfigures the optical circuit switch based on a configuration of the removable line cards to maintain a guaranteed packet switching bandwidth between active line cards.
摘要翻译：如本文所述，网络设备包括执行电路交换的光电路开关。网络设备还具有多个可拆卸线路卡，每个线路卡包括分组交换机。切换管理器基于可移除线路卡的配置自动重新配置光电开关，以在有源线路卡之间维持保证的分组交换带宽。

7. 发明申请

US20110010525A1 On-chip and Chip-to-chip Routing Using a Processor Element/Router Combination 有权
标题翻译：使用处理器元件/路由器组合的片上和芯片到芯片路由
公开(公告)号：US20110010525A1
公开(公告)日：2011-01-13
申请号：US12501000
申请日：2009-07-10
申请人： Nathan Binkert , Moray McLaren
发明人： Nathan Binkert , Moray McLaren
IPC分类号： G06F15/76 , G06F9/02
CPC分类号： G06F15/17343 , G06F15/7825
摘要： A system and method is shown for on-chip and chip-to-chip routing. The system and method includes a processor element residing on a processor die to process a data packet received at the processor die. The system and method also include a router residing on the process die to route the data packet received at the processor die. Further, the system and method includes a switch core residing on the processor die to switch a communication channel along which the data packet is to be transmitted. Additionally, the system and method includes a switch core to identify a destination processing element and router (PE/R) module for a data packet, the switch core and the destination PE/R module residing on a common processor die. Moreover, the system and method includes a communication channel to operatively connect the switch core and the destination PE/R module on the common processor die.
摘要翻译：显示了用于片上和芯片到芯片布线的系统和方法。该系统和方法包括驻留在处理器管芯上以处理在处理器管芯处接收的数据包的处理器元件。系统和方法还包括驻留在处理管芯上的路由器来路由在处理器管芯处接收的数据分组。此外，该系统和方法包括位于处理器管芯上的交换机核心，用于切换数据分组将被发送的通信信道。另外，该系统和方法包括一个交换机核心，用于识别驻留在公共处理器管芯上的数据包，交换机核心和目的PE / R模块的目的地处理元件和路由器（PE / R）模块。此外，该系统和方法包括一个通信信道，用于将公共处理器管芯上的交换机核心和目的PE / R模块连接起来。

8. 发明授权

US08942559B2 Switching in a network device 有权
标题翻译：切换网络设备
公开(公告)号：US08942559B2
公开(公告)日：2015-01-27
申请号：US13696631
申请日：2010-05-20
申请人： Nathan Binkert , Moray McLaren , Michael Tan
发明人： Nathan Binkert , Moray McLaren , Michael Tan
IPC分类号： H04J14/00 , H04L12/24 , H04L12/937 , H04L12/935 , H04L12/931
CPC分类号： H04L41/0826 , H04L49/253 , H04L49/30 , H04L49/40 , H04Q11/0066 , H04Q11/0071 , H04Q2011/0081
摘要： As described herein, a network device includes an optical circuit switch to perform circuit switching. The network device also has a plurality of removable line cards, each of which includes a packet switch. A switching manager automatically reconfigures the optical circuit switch based on a configuration of the removable line cards to maintain a guaranteed packet switching bandwidth between active line cards.
摘要翻译：如本文所述，网络设备包括执行电路交换的光电路开关。网络设备还具有多个可拆卸线路卡，每个线路卡包括分组交换机。切换管理器基于可移除线路卡的配置自动重新配置光电开关，以在有源线路卡之间维持保证的分组交换带宽。

9. 发明授权

US08938139B2 Optoelectronic switches using on-chip optical waveguides 有权
标题翻译：使用片上光波导的光电开关
公开(公告)号：US08938139B2
公开(公告)日：2015-01-20
申请号：US12921768
申请日：2008-03-11
申请人： Moray McLaren , Jung Ho Ahn , Nathan L. Binkert , Alan L. Davis , Norman Paul Jouppi
发明人： Moray McLaren , Jung Ho Ahn , Nathan L. Binkert , Alan L. Davis , Norman Paul Jouppi
IPC分类号： G02B6/26 , G02B6/12 , G02F1/313 , H04Q11/00 , G02B6/293 , G02B6/35
CPC分类号： G02B6/12007 , G02B6/29338 , G02B6/35 , G02B6/3546 , G02B6/356 , G02F1/3137 , G02F1/3138 , G02F2201/17 , G02F2202/32 , G02F2203/15 , H04Q11/0005 , H04Q11/0066 , H04Q2011/0016 , H04Q2011/0035 , H04Q2011/0058
摘要： Embodiments of the present invention are directed to optoelectronic network switches. In one embodiment, an optoelectronic switch includes a set of roughly parallel input waveguides and a set of roughly parallel output waveguides positioned roughly perpendicular to the input waveguides. Each of the output waveguides crosses the set of input waveguides. The optoelectronic switch includes at least one switch element configured to switch one or more optical signals transmitted on one or more input waveguides onto one or more crossing output waveguides.
摘要翻译：本发明的实施例涉及光电网络交换机。在一个实施例中，光电开关包括一组大致平行的输入波导和大致垂直于输入波导定位的大致平行的输出波导组。每个输出波导穿过该组输入波导。光电开关包括至少一个开关元件，其被配置为将在一个或多个输入波导上传输的一个或多个光信号切换到一个或多个交叉输出波导上。

10. 发明授权

US08059443B2 Three-dimensional memory module architectures 有权
标题翻译：三维内存模块架构
公开(公告)号：US08059443B2
公开(公告)日：2011-11-15
申请号：US11975963
申请日：2007-10-23
申请人： Moray McLaren , Jung Ho Ahn , Alan Lynn Davis , Nathan Lorenzo Binkert , Norman Paul Jouppi
发明人： Moray McLaren , Jung Ho Ahn , Alan Lynn Davis , Nathan Lorenzo Binkert , Norman Paul Jouppi
IPC分类号： G11C13/04
CPC分类号： G11C5/04 , G11C5/02 , G11C5/025 , G11C13/04 , G11C2211/4016 , G11C2213/71 , H01L25/0657 , H01L25/18 , H01L2225/06534 , H01L2225/06541 , H01L2225/06565 , H01L2924/0002 , H01L2924/15311 , H01L2924/00
摘要： Various embodiments of the present invention are directed to stacked memory modules. In one embodiment of the present invention, a memory module comprises at least one memory-controller layer stacked with at least one memory layer. Fine pitched through vias (e.g., through silicon vias) extend approximately perpendicular to a surface of the at least one memory controller through the stack providing electronic communication between the at least one memory controller and the at least one memory layers. Additionally, the memory-controller layer includes at least one external interface configured to transmit data to and from the memory module. Furthermore, the memory module can include an optical layer. The optical layer can be included in the stack and has a bus waveguide to transmit data to and from the at least one memory controller. The external interface can be an optical external interface which interfaces with the optical layer.
摘要翻译：本发明的各种实施例涉及堆叠的存储器模块。在本发明的一个实施例中，存储器模块包括至少一个堆叠有至少一个存储器层的存储器 - 控制器层。通过通孔（例如，通过硅通孔）精细地延伸通过堆叠大致垂直于至少一个存储器控制器的表面延伸，从而提供至少一个存储器控制器与至少一个存储器层之间的电子通信。此外，存储器控制器层包括被配置为向存储器模块传送数据和从存储器模块传送数据的至少一个外部接口。此外，存储器模块可以包括光学层。光学层可以被包括在堆叠中并且具有总线波导以将数据传送到至少一个存储器控制器和从至少一个存储器控制器传送数据。外部接口可以是与光学层接口的光学外部接口。

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