专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08168535B2 Method fabricating semiconductor device using multiple polishing processes 有权
标题翻译：使用多次抛光工艺制造半导体器件的方法
公开(公告)号：US08168535B2
公开(公告)日：2012-05-01
申请号：US13084657
申请日：2011-04-12
申请人： Jun-Soo Bae , Suk-Hun Choi , Won-Jun Lee , Joon-Sang Park
发明人： Jun-Soo Bae , Suk-Hun Choi , Won-Jun Lee , Joon-Sang Park
IPC分类号： H01L21/44
CPC分类号： H01L45/1683 , H01L45/06 , H01L45/141
摘要： A method of fabricating a phase change memory device includes the use of first, second and third polishing processes. The first polishing process forms a first contact portion using a first sacrificial layer and the second polishing process forms a phase change material pattern using a second sacrificial layer. After removing the first and second sacrificial layers to expose resultant protruding structures of the first contact portion and the phase change material pattern, a third polishing process is used to polish the resultant protruding structures using an insulation layer as a polishing stopper layer.
摘要翻译：制造相变存储器件的方法包括使用第一，第二和第三抛光工艺。第一抛光工艺使用第一牺牲层形成第一接触部分，并且第二抛光工艺使用第二牺牲层形成相变材料图案。在去除第一和第二牺牲层以暴露第一接触部分的相应突出结构和相变材料图案之后，使用第三抛光工艺来使用绝缘层作为抛光停止层来抛光所得的突出结构。

2. 发明授权

US07291556B2 Method for forming small features in microelectronic devices using sacrificial layers 失效
标题翻译：在使用牺牲层的微电子器件中形成小特征的方法
公开(公告)号：US07291556B2
公开(公告)日：2007-11-06
申请号：US10873388
申请日：2004-06-22
申请人： Suk-Hun Choi , Yoon-Ho Son , Sung-Lae Cho , Joon-Sang Park
发明人： Suk-Hun Choi , Yoon-Ho Son , Sung-Lae Cho , Joon-Sang Park
IPC分类号： H01L21/00
CPC分类号： H01L45/06 , H01L27/2436 , H01L45/1233 , H01L45/126 , H01L45/16
摘要： A dielectric layer is formed on a region of a microelectronic substrate. A sacrificial layer is formed on the dielectric layer, and portions of the sacrificial layer and the dielectric layer are removed to form an opening that exposes a portion of the region. A conductive layer is formed on the sacrificial layer and in the opening. Portions of the sacrificial layer and the conductive layer on the dielectric layer are removed to leave a conductive plug in the dielectric layer and in contact with the region. Removal of the sacrificial layer and portions of the conductive layer on the dielectric layer may include polishing to expose the sacrificial layer and to leave a conductive plug in the sacrificial layer and the dielectric layer, etching the sacrificial layer to expose the dielectric layer and leave a portion of the conductive plug protruding from the dielectric layer, and polishing to remove the protruding portion of the conductive plug. Phase-change memory devices formed by such techniques are also discussed.
摘要翻译：在微电子基板的区域上形成介电层。在电介质层上形成牺牲层，去除牺牲层和电介质层的部分以形成露出该区域的一部分的开口。在牺牲层和开口中形成导电层。去除部分牺牲层和电介质层上的导电层，以在电介质层中留下导电插塞并与该区域接触。消除牺牲层和电介质层上的导电层的部分可以包括抛光以暴露牺牲层并且在牺牲层和电介质层中留下导电插塞，蚀刻牺牲层以暴露电介质层并留下导电插头从电介质层突出的部分，并且抛光以去除导电插塞的突出部分。还讨论了通过这种技术形成的相变存储器件。

3. 发明申请

US20080011999A1 Microelectronic Devices Using Sacrificial Layers and Structures Fabricated by Same 有权
标题翻译：使用牺牲层的微电子器件和由其制造的结构
公开(公告)号：US20080011999A1
公开(公告)日：2008-01-17
申请号：US11860674
申请日：2007-09-25
申请人： Suk-Hun Choi , Yoon-Ho Son , Sung-Lae Cho , Joon-Sang Park
发明人： Suk-Hun Choi , Yoon-Ho Son , Sung-Lae Cho , Joon-Sang Park
IPC分类号： H01L45/00
CPC分类号： H01L45/06 , H01L27/2436 , H01L45/1233 , H01L45/126 , H01L45/16
摘要： A dielectric layer is formed on a region of a microelectronic substrate. A sacrificial layer is formed on the dielectric layer, and portions of the sacrificial layer and the dielectric layer are removed to form an opening that exposes a portion of the region. A conductive layer is formed on the sacrificial layer and in the opening. Portions of the sacrificial layer and the conductive layer on the dielectric layer are removed to leave a conductive plug in the dielectric layer and in contact with the region. Removal of the sacrificial layer and portions of the conductive layer on the dielectric layer may include polishing to expose the sacrificial layer and to leave a conductive plug in the sacrificial layer and the dielectric layer, etching the sacrificial layer to expose the dielectric layer and leave a portion of the conductive plug protruding from the dielectric layer, and polishing to remove the protruding portion of the conductive plug. Phase-change memory devices formed by such techniques are also discussed.
摘要翻译：在微电子基板的区域上形成介电层。在电介质层上形成牺牲层，去除牺牲层和电介质层的部分以形成露出该区域的一部分的开口。在牺牲层和开口中形成导电层。去除部分牺牲层和电介质层上的导电层，以在电介质层中留下导电插塞并与该区域接触。消除牺牲层和电介质层上的导电层的部分可以包括抛光以暴露牺牲层并在牺牲层和电介质层中留下导电插塞，蚀刻牺牲层以暴露电介质层并留下导电插头从电介质层突出的部分，并且抛光以去除导电插塞的突出部分。还讨论了通过这种技术形成的相变存储器件。

4. 发明申请

US20050130414A1 Methods for forming small features in microelectronic devices using sacrificial layers and structures fabricated by same 失效
标题翻译：在使用牺牲层和由其制造的结构的微电子器件中形成小特征的方法
公开(公告)号：US20050130414A1
公开(公告)日：2005-06-16
申请号：US10873388
申请日：2004-06-22
申请人： Suk-Hun Choi , Yoon-Ho Son , Sung-Lae Cho , Joon-Sang Park
发明人： Suk-Hun Choi , Yoon-Ho Son , Sung-Lae Cho , Joon-Sang Park
IPC分类号： H01L21/28 , H01L21/20 , H01L21/44 , H01L27/24 , H01L45/00
CPC分类号： H01L45/06 , H01L27/2436 , H01L45/1233 , H01L45/126 , H01L45/16
摘要： A dielectric layer is formed on a region of a microelectronic substrate. A sacrificial layer is formed on the dielectric layer, and portions of the sacrificial layer and the dielectric layer are removed to form an opening that exposes a portion of the region. A conductive layer is formed on the sacrificial layer and in the opening. Portions of the sacrificial layer and the conductive layer on the dielectric layer are removed to leave a conductive plug in the dielectric layer and in contact with the region. Removal of the sacrificial layer and portions of the conductive layer on the dielectric layer may include polishing to expose the sacrificial layer and to leave a conductive plug in the sacrificial layer and the dielectric layer, etching the sacrificial layer to expose the dielectric layer and leave a portion of the conductive plug protruding from the dielectric layer, and polishing to remove the protruding portion of the conductive plug. Phase-change memory devices formed by such techniques are also discussed.
摘要翻译：在微电子基板的区域上形成介电层。在电介质层上形成牺牲层，去除牺牲层和电介质层的部分以形成露出该区域的一部分的开口。在牺牲层和开口中形成导电层。去除部分牺牲层和电介质层上的导电层，以在电介质层中留下导电插塞并与该区域接触。消除牺牲层和电介质层上的导电层的部分可以包括抛光以暴露牺牲层并在牺牲层和电介质层中留下导电插塞，蚀刻牺牲层以暴露电介质层并留下导电插头从电介质层突出的部分，并且抛光以去除导电插塞的突出部分。还讨论了通过这种技术形成的相变存储器件。

5. 发明申请

US20050127347A1 Methods for fabricating memory devices using sacrificial layers and memory devices fabricated by same 有权
标题翻译：用于制造使用牺牲层的存储器件和由其制造的存储器件的方法
公开(公告)号：US20050127347A1
公开(公告)日：2005-06-16
申请号：US10999103
申请日：2004-11-29
申请人： Suk-Hun Choi , Yoon-Ho Son , Sung-Lae Cho , Joon-Sang Park
发明人： Suk-Hun Choi , Yoon-Ho Son , Sung-Lae Cho , Joon-Sang Park
IPC分类号： H01L21/4763 , H01L21/768 , H01L27/24 , H01L29/40
CPC分类号： H01L21/76816 , H01L21/76831 , H01L21/7684 , H01L21/76883 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/126
摘要： A protection layer is formed on a semiconductor substrate having a cell array region and an alignment key region. A plurality of data storage elements are formed on the protection layer in the cell array region. An insulating layer is formed on the data storage elements, a barrier layer is formed on the insulating layer, and a sacrificial layer is formed on the barrier layer. The sacrificial layer, the barrier layer and the insulating layer are patterned to form contact holes that expose the data storage elements, and conductive plugs are formed in the contact holes. The sacrificial layer is etched to leave portions of the conductive plugs protruding from the barrier layer. The protruding portions of the conductive plugs are removed by polishing.
摘要翻译：在具有单元阵列区域和对准键区域的半导体基板上形成保护层。在单元阵列区域的保护层上形成多个数据存储元件。在数据存储元件上形成绝缘层，在绝缘层上形成阻挡层，在势垒层上形成牺牲层。牺牲层，阻挡层和绝缘层被图案化以形成暴露数据存储元件的接触孔，并且在接触孔中形成导电插塞。蚀刻牺牲层以使导电塞从阻挡层突出的部分。通过抛光去除导电塞的突出部分。

6. 发明申请

US20070284743A1 Fabricating Memory Devices Using Sacrificial Layers and Memory Devices Fabricated by Same 审中-公开
标题翻译：使用由相同的制造的牺牲层和存储器件来制造存储器件
公开(公告)号：US20070284743A1
公开(公告)日：2007-12-13
申请号：US11832282
申请日：2007-08-01
申请人： Suk-Hun Choi , Yoon-Ho Son , Sung-Lae Cho , Joon-Sang Park
发明人： Suk-Hun Choi , Yoon-Ho Son , Sung-Lae Cho , Joon-Sang Park
IPC分类号： H01L23/52
CPC分类号： H01L27/24
摘要： A protection layer is formed on a semiconductor substrate having a cell array region and an alignment key region. A plurality of data storage elements are formed on the protection layer in the cell array region. An insulating layer is formed on the data storage elements, a barrier layer is formed on the insulating layer, and a sacrificial layer is formed on the barrier layer. The sacrificial layer, the barrier layer and the insulating layer are patterned to form contact holes that expose the data storage elements, and conductive plugs are formed in the contact holes. The sacrificial layer is etched to leave portions of the conductive plugs protruding from the barrier layer. The protruding portions of the conductive plugs are removed by polishing.
摘要翻译：在具有单元阵列区域和对准键区域的半导体基板上形成保护层。在单元阵列区域的保护层上形成多个数据存储元件。在数据存储元件上形成绝缘层，在绝缘层上形成阻挡层，在势垒层上形成牺牲层。牺牲层，阻挡层和绝缘层被图案化以形成暴露数据存储元件的接触孔，并且在接触孔中形成导电插塞。蚀刻牺牲层以使导电塞从阻挡层突出的部分。通过抛光去除导电塞的突出部分。

7. 发明授权

US07265050B2 Methods for fabricating memory devices using sacrificial layers 有权
标题翻译：使用牺牲层制造存储器件的方法
公开(公告)号：US07265050B2
公开(公告)日：2007-09-04
申请号：US10999103
申请日：2004-11-29
申请人： Suk-Hun Choi , Yoon-Ho Son , Sung-Lae Cho , Joon-Sang Park
发明人： Suk-Hun Choi , Yoon-Ho Son , Sung-Lae Cho , Joon-Sang Park
IPC分类号： H01L21/00
CPC分类号： H01L21/76816 , H01L21/76831 , H01L21/7684 , H01L21/76883 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/126
摘要： A protection layer is formed on a semiconductor substrate having a cell array region and an alignment key region. A plurality of data storage elements are formed on the protection layer in the cell array region. An insulating layer is formed on the data storage elements, a barrier layer is formed on the insulating layer, and a sacrificial layer is formed on the barrier layer. The sacrificial layer, the barrier layer and the insulating layer are patterned to form contact holes that expose the data storage elements, and conductive plugs are formed in the contact holes. The sacrificial layer is etched to leave portions of the conductive plugs protruding from the barrier layer. The protruding portions of the conductive plugs are removed by polishing.
摘要翻译：在具有单元阵列区域和对准键区域的半导体基板上形成保护层。在单元阵列区域的保护层上形成多个数据存储元件。在数据存储元件上形成绝缘层，在绝缘层上形成阻挡层，在势垒层上形成牺牲层。牺牲层，阻挡层和绝缘层被图案化以形成暴露数据存储元件的接触孔，并且在接触孔中形成导电插塞。蚀刻牺牲层以使导电塞从阻挡层突出的部分。通过抛光去除导电塞的突出部分。

8. 发明授权

US07612359B2 Microelectronic devices using sacrificial layers and structures fabricated by same 有权
标题翻译：使用牺牲层的微电子器件和由其制造的结构
公开(公告)号：US07612359B2
公开(公告)日：2009-11-03
申请号：US11860674
申请日：2007-09-25
申请人： Suk-Hun Choi , Yoon-Ho Son , Sung-Lae Cho , Joon-Sang Park
发明人： Suk-Hun Choi , Yoon-Ho Son , Sung-Lae Cho , Joon-Sang Park
IPC分类号： H01L29/02
CPC分类号： H01L45/06 , H01L27/2436 , H01L45/1233 , H01L45/126 , H01L45/16
摘要： A dielectric layer is formed on a region of a microelectronic substrate. A sacrificial layer is formed on the dielectric layer, and portions of the sacrificial layer and the dielectric layer are removed to form an opening that exposes a portion of the region. A conductive layer is formed on the sacrificial layer and in the opening. Portions of the sacrificial layer and the conductive layer on the dielectric layer are removed to leave a conductive plug in the dielectric layer and in contact with the region. Removal of the sacrificial layer and portions of the conductive layer on the dielectric layer may include polishing to expose the sacrificial layer and to leave a conductive plug in the sacrificial layer and the dielectric layer, etching the sacrificial layer to expose the dielectric layer and leave a portion of the conductive plug protruding from the dielectric layer, and polishing to remove the protruding portion of the conductive plug. Phase-change memory devices formed by such techniques are also discussed.
摘要翻译：在微电子基板的区域上形成介电层。在电介质层上形成牺牲层，去除牺牲层和电介质层的部分以形成露出该区域的一部分的开口。在牺牲层和开口中形成导电层。去除部分牺牲层和电介质层上的导电层，以在电介质层中留下导电插塞并与该区域接触。消除牺牲层和电介质层上的导电层的部分可以包括抛光以暴露牺牲层并在牺牲层和电介质层中留下导电插塞，蚀刻牺牲层以暴露电介质层并留下导电插头从电介质层突出的部分，并且抛光以去除导电插塞的突出部分。还讨论了通过这种技术形成的相变存储器件。

9. 发明授权

US08288289B2 Method of fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08288289B2
公开(公告)日：2012-10-16
申请号：US13016228
申请日：2011-01-28
申请人： Jun-Ho Jeong , Jang-Eun Lee , Se-Chung Oh , Suk-Hun Choi , Jea-Hyoung Lee , Woo-Jin Kim , Woo-Chang Lim
发明人： Jun-Ho Jeong , Jang-Eun Lee , Se-Chung Oh , Suk-Hun Choi , Jea-Hyoung Lee , Woo-Jin Kim , Woo-Chang Lim
IPC分类号： H01L21/302
CPC分类号： H01L21/28
摘要： A method of fabricating a semiconductor device, the method including providing a substrate; forming an underlying layer on the substrate; forming a sacrificial layer on the underlying layer; forming an opening in the sacrificial layer by patterning the sacrificial layer such that the opening exposes a predetermined region of the underlying layer; forming a mask layer in the opening; forming an oxide mask by partially or completely oxidizing the mask layer; removing the sacrificial layer; and etching the underlying layer using the oxide mask as an etch mask to form an underlying layer pattern.
摘要翻译：一种制造半导体器件的方法，所述方法包括提供衬底; 在衬底上形成下层; 在下层上形成牺牲层; 通过图案化所述牺牲层在所述牺牲层中形成开口，使得所述开口暴露所述下层的预定区域; 在开口中形成掩模层; 通过部分或完全氧化掩模层形成氧化物掩模; 去除牺牲层; 并使用氧化物掩模作为蚀刻掩模蚀刻下层以形成下层图案。

10. 发明授权

US08168521B2 Methods of manufacturing semiconductor devices having low resistance buried gate structures 有权
标题翻译：制造具有低电阻掩埋栅极结构的半导体器件的方法
公开(公告)号：US08168521B2
公开(公告)日：2012-05-01
申请号：US12725743
申请日：2010-03-17
申请人： In-Sang Jeon , Si-Hyung Lee , Jong-Ryeol Yoo , Yu-Ghun Shin , Suk-Hun Choi
发明人： In-Sang Jeon , Si-Hyung Lee , Jong-Ryeol Yoo , Yu-Ghun Shin , Suk-Hun Choi
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L29/4236 , H01L21/67207 , H01L21/823437 , H01L21/823456 , H01L29/66621 , H01L29/78
摘要： In a method of manufacturing a semiconductor device, a recess is formed in an active region of a substrate. A gate insulation layer is formed in the first recess. A barrier layer is formed on the gate insulation layer. A preliminary nucleation layer having a first resistance is formed on the barrier layer. The preliminary nucleation layer is converted into a nucleation layer having a second resistance substantially smaller than the first resistance. A conductive layer is formed on the nucleation layer. The conductive layer, the nucleation layer, the barrier layer and the gate insulation layer are partially etched to form a buried gate structure including a gate insulation layer pattern, a barrier layer pattern, a nucleation layer pattern and a conductive layer pattern.
摘要翻译：在制造半导体器件的方法中，在衬底的有源区中形成凹部。在第一凹部中形成栅极绝缘层。在栅绝缘层上形成阻挡层。在阻挡层上形成具有第一电阻的预成核层。将初始成核层转变成具有比第一电阻显着小的第二电阻的成核层。在成核层上形成导电层。部分蚀刻导电层，成核层，势垒层和栅极绝缘层，以形成包括栅极绝缘层图案，势垒层图案，成核层图案和导电层图案的掩埋栅极结构。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式