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1. 发明申请

US20100289085A1 Asymmetric Semiconductor Devices and Method of Fabricating 失效
标题翻译：不对称半导体器件及其制造方法
公开(公告)号：US20100289085A1
公开(公告)日：2010-11-18
申请号：US12465818
申请日：2009-05-14
申请人： Jun Yuan , Dureseti Chidambarrao , Sunfei Fang , Haizhou Yin , Yue Liang , Xiaojun Yu
发明人： Jun Yuan , Dureseti Chidambarrao , Sunfei Fang , Haizhou Yin , Yue Liang , Xiaojun Yu
IPC分类号： H01L27/092 , H01L29/78 , H01L21/336
CPC分类号： H01L29/4983 , H01L21/28114 , H01L21/28132 , H01L29/42368 , H01L29/42376 , H01L29/513 , H01L29/6659 , H01L29/7835 , Y10S257/90
摘要： A semiconductor structure is provided that includes an asymmetric gate stack located on a surface of high k gate dielectric. The asymmetric gate stack includes a first portion and a second portion, wherein the first portion has a different threshold voltage than the second portion. The first portion of the inventive asymmetric gate stack includes, from bottom to top, a threshold voltage adjusting material and at least a first conductive spacer, while the second portion of the inventive asymmetric gate stack includes at least a second conductive spacer over the gate dielectric. In some embodiments, the second conductive spacer is in direct contact with the underlying high k gate dielectric, while in other embodiments, in which the first and second conductive spacers are comprised of different conductive materials, the base of the second conductive spacer is in direct contact with the threshold adjusting material.
摘要翻译：提供了一种半导体结构，其包括位于高k栅极电介质的表面上的非对称栅极堆叠。非对称栅极堆叠包括第一部分和第二部分，其中第一部分具有与第二部分不同的阈值电压。本发明的不对称栅极堆叠的第一部分包括从底部到顶部的阈值电压调节材料和至少第一导电间隔物，而本发明的不对称栅极堆叠的第二部分包括在栅极电介质上的至少第二导电间隔物。在一些实施例中，第二导电间隔物与下面的高k栅极电介质直接接触，而在其它实施例中，第一和第二导电间隔物由不同的导电材料构成，第二导电间隔物的基底直接接触阈值调节材料。

2. 发明授权

US07999332B2 Asymmetric semiconductor devices and method of fabricating 失效
标题翻译：非对称半导体器件及其制造方法
公开(公告)号：US07999332B2
公开(公告)日：2011-08-16
申请号：US12465818
申请日：2009-05-14
申请人： Jun Yuan , Dureseti Chidambarrao , Sunfei Fang , Yue Liang , Haizhou Yin , Xiaojun Yu
发明人： Jun Yuan , Dureseti Chidambarrao , Sunfei Fang , Yue Liang , Haizhou Yin , Xiaojun Yu
IPC分类号： H01L21/70
CPC分类号： H01L29/4983 , H01L21/28114 , H01L21/28132 , H01L29/42368 , H01L29/42376 , H01L29/513 , H01L29/6659 , H01L29/7835 , Y10S257/90
摘要： A semiconductor structure is provided that includes an asymmetric gate stack located on a surface of high k gate dielectric. The asymmetric gate stack includes a first portion and a second portion, wherein the first portion has a different threshold voltage than the second portion. The first portion of the inventive asymmetric gate stack includes, from bottom to top, a threshold voltage adjusting material and at least a first conductive spacer, while the second portion of the inventive asymmetric gate stack includes at least a second conductive spacer over the gate dielectric. In some embodiments, the second conductive spacer is in direct contact with the underlying high k gate dielectric, while in other embodiments, in which the first and second conductive spacers are comprised of different conductive materials, the base of the second conductive spacer is in direct contact with the threshold adjusting material.
摘要翻译：提供了一种半导体结构，其包括位于高k栅极电介质的表面上的非对称栅极堆叠。非对称栅极堆叠包括第一部分和第二部分，其中第一部分具有与第二部分不同的阈值电压。本发明的不对称栅极堆叠的第一部分包括从底部到顶部的阈值电压调节材料和至少第一导电间隔物，而本发明的不对称栅极堆叠的第二部分包括在栅极电介质上的至少第二导电间隔物。在一些实施例中，第二导电间隔物与下面的高k栅极电介质直接接触，而在其它实施例中，第一和第二导电间隔物由不同的导电材料构成，第二导电间隔物的基底直接接触阈值调节材料。

3. 发明授权

US08643061B2 Structure of high-K metal gate semiconductor transistor 有权
标题翻译：高K金属栅半导体晶体管的结构
公开(公告)号：US08643061B2
公开(公告)日：2014-02-04
申请号：US12908024
申请日：2010-10-20
申请人： Haizhou Yin , Dae-Gyu Park , Oleg Gluschenkov , Zhijiong Luo , Dominic Schepis , Jun Yuan
发明人： Haizhou Yin , Dae-Gyu Park , Oleg Gluschenkov , Zhijiong Luo , Dominic Schepis , Jun Yuan
IPC分类号： H01L29/66
CPC分类号： H01L21/84 , H01L21/76254 , H01L21/823807 , H01L21/823878 , H01L27/1203 , H01L29/1054 , H01L29/66651 , H01L29/78
摘要： A semiconductor structure is provided. The structure includes an n-type field-effect-transistor (NFET) being formed directly on top of a strained silicon layer, and a p-type field-effect-transistor (PFET) being formed on top of the same stained silicon layer but via a layer of silicon-germanium (SiGe). The strained silicon layer may be formed on top of a layer of insulating material or a silicon-germanium layer with graded Ge content variation. Furthermore, the NFET and PFET are formed next to each other and are separated by a shallow trench isolation (STI) formed inside the strained silicon layer. Methods of forming the semiconductor structure are also provided.
摘要翻译：提供半导体结构。该结构包括直接形成在应变硅层的顶部上的n型场效应晶体管（NFET），以及形成在同一染色硅层顶部的p型场效应晶体管（PFET），但是通过一层硅 - 锗（SiGe）。应变硅层可以形成在具有分级Ge含量变化的绝缘材料层或硅 - 锗层的顶部上。此外，NFET和PFET彼此相邻形成，并且通过形成在应变硅层内部的浅沟槽隔离（STI）分开。还提供了形成半导体结构的方法。

4. 发明申请

US20120098067A1 STRUCTURE OF HIGH-K METAL GATE SEMICONDUCTOR TRANSISTOR 有权
标题翻译：高K金属栅极半导体晶体管的结构
公开(公告)号：US20120098067A1
公开(公告)日：2012-04-26
申请号：US12908024
申请日：2010-10-20
申请人： Haizhou Yin , Dae-Gyu Park , Oleg Gluschenkov , Zhijiong Luo , Dominic Schepis , Jun Yuan
发明人： Haizhou Yin , Dae-Gyu Park , Oleg Gluschenkov , Zhijiong Luo , Dominic Schepis , Jun Yuan
IPC分类号： H01L27/092 , H01L27/12
CPC分类号： H01L21/84 , H01L21/76254 , H01L21/823807 , H01L21/823878 , H01L27/1203 , H01L29/1054 , H01L29/66651 , H01L29/78
摘要： A semiconductor structure is provided. The structure includes an n-type field-effect-transistor (NFET) being formed directly on top of a strained silicon layer, and a p-type field-effect-transistor (PFET) being formed on top of the same stained silicon layer but via a layer of silicon-germanium (SiGe). The strained silicon layer may be formed on top of a layer of insulating material or a silicon-germanium layer with graded Ge content variation. Furthermore, the NFET and PFET are formed next to each other and are separated by a shallow trench isolation (STI) formed inside the strained silicon layer. Methods of forming the semiconductor structure are also provided.
摘要翻译：提供半导体结构。该结构包括直接在应变硅层的顶部形成的n型场效应晶体管（NFET），以及形成在同一染色硅层顶部的p型场效应晶体管（PFET），但是通过一层硅 - 锗（SiGe）。应变硅层可以形成在具有分级Ge含量变化的绝缘材料层或硅 - 锗层的顶部上。此外，NFET和PFET彼此相邻形成，并且通过形成在应变硅层内部的浅沟槽隔离（STI）分开。还提供了形成半导体结构的方法。

5. 发明授权

US09614050B2 Method for manufacturing semiconductor devices 有权
公开(公告)号：US09614050B2
公开(公告)日：2017-04-04
申请号：US14414355
申请日：2012-08-06
申请人： Haizhou Yin , Keke Zhang
发明人： Haizhou Yin , Keke Zhang
IPC分类号： H01L21/337 , H01L29/66 , H01L21/768 , H01L21/285
CPC分类号： H01L29/66492 , H01L21/28518 , H01L21/76897 , H01L29/66583 , H01L29/6659
摘要： The present invention provides a method for manufacturing a semiconductor device, comprising: forming a contact sacrificial pattern on a substrate to cover source and drain regions and expose a gate region; forming an interlayer dielectric layer on the substrate to cover the contact sacrificial pattern and expose the gate region; forming a gate stack structure in the exposed gate region; removing the contact sacrificial pattern to form the source/drain contact trench; and forming a source/drain contact in the source/drain contact trench. By means of a contact sacrificial layer process, the method of manufacturing a semiconductor device according to the present invention effectively reduces the distance between the gate spacer and the contact region and increases the area of the contact region, thus effectively reducing the parasitic resistance of the device.

6. 发明授权

US09576802B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09576802B2
公开(公告)日：2017-02-21
申请号：US14412173
申请日：2012-07-19
申请人： Haizhou Yin , Huilong Zhu , Keke Zhang
发明人： Haizhou Yin , Huilong Zhu , Keke Zhang
IPC分类号： H01L21/331 , H01L21/28 , H01L29/66 , H01L21/3105 , H01L29/78 , H01L29/423 , H01L29/417
CPC分类号： H01L21/28114 , H01L21/28088 , H01L21/31051 , H01L29/41783 , H01L29/42376 , H01L29/4966 , H01L29/6653 , H01L29/66545 , H01L29/6659 , H01L29/66628 , H01L29/78 , H01L29/7834
摘要： A method for manufacturing a semiconductor device is disclosed. The method comprises: forming a T-shape dummy gate structure on the substrate; removing the T-shape dummy gate structure and retaining a T-shape gate trench; forming a T-shape metal gate structure by filling a metal layer in the T-shape gate trench. According to the semiconductor device manufacturing method disclosed in the present application, the overhang phenomenon and the formation of voids are avoided in the subsequent metal gate filling process by forming a T-shape dummy gate and a T-shape gate trench, and the device performance is improved.
摘要翻译：公开了一种制造半导体器件的方法。该方法包括：在衬底上形成T形虚拟栅极结构; 去除T形虚拟栅极结构并保持T形栅极沟槽; 通过在T形栅极沟槽中填充金属层来形成T形金属栅极结构。根据本申请中公开的半导体器件制造方法，通过形成T形虚拟栅极和T形栅极沟槽，在随后的金属栅极填充处理中避免了突出现象和空隙的形成，并且器件性能改进了

7. 发明授权

US09356025B2 Enhancing MOSFET performance with corner stresses of STI 有权
标题翻译：通过STI拐角应力增强MOSFET性能
公开(公告)号：US09356025B2
公开(公告)日：2016-05-31
申请号：US14348579
申请日：2012-03-29
申请人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L27/092 , H01L29/78 , H01L21/8238 , H01L21/762 , H01L29/66
CPC分类号： H01L27/092 , H01L21/76224 , H01L21/823807 , H01L21/823878 , H01L29/66575 , H01L29/7846
摘要： The present invention relates to enhancing MOSFET performance with the corner stresses of STI. A method of manufacturing a MOS device comprises the steps of: providing a semiconductor substrate; forming trenches on the semiconductor substrate and at least a pMOS region and at least an nMOS region surrounded by the trenches; filling the trenches with a dielectric material having a stress; removing at least the dielectric material having a stress in the trenches which is adjacent to a position where a channel is to be formed on each of the pMOS and nMOS regions so as to form exposed regions; filling the exposed regions with a insulating material; and forming pMOS and nMOS devices on the pMOS region and the nMOS region, respectively, wherein each of the pMOS and nMOS devices comprises a channel, a gate formed above the channel, and a source and a drain formed at both sides of the channel; wherein in a channel length direction, the boundary of each exposed region is substantially aligned with the boundary of the position of the channel, or the boundary of each exposed region extends along the channel length direction to be aligned with the boundary of corresponding pMOS or nMOS region.
摘要翻译：本发明涉及利用STI的拐角应力来增强MOSFET的性能。一种制造MOS器件的方法包括以下步骤：提供半导体衬底; 在所述半导体衬底和至少一个pMOS区域和由所述沟槽包围的至少nMOS区域中形成沟槽; 用具有应力的介电材料填充沟槽; 至少去除在沟道中具有应力的介电材料，所述沟槽邻近要在pMOS和nMOS区域中的每一个上形成沟道的位置，以形成暴露区域; 用绝缘材料填充暴露的区域; 以及分别在pMOS区域和nMOS区域上形成pMOS和nMOS器件，其中pMOS和nMOS器件中的每一个包括沟道，形成在沟道上方的栅极以及形成在沟道两侧的源极和漏极; 其中在通道长度方向上，每个曝光区域的边界基本上与通道位置的边界对齐，或者每个曝光区域的边界沿着沟道长度方向延伸以与对应的pMOS或nMOS的边界对准地区。

8. 发明授权

US09054221B2 Semiconductor device with a common back gate isolation region and method for manufacturing the same 有权
标题翻译：具有公共背栅隔离区的半导体器件及其制造方法
公开(公告)号：US09054221B2
公开(公告)日：2015-06-09
申请号：US13510807
申请日：2011-11-18
申请人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L27/088 , H01L21/336 , H01L21/84 , H01L27/12
CPC分类号： H01L21/84 , H01L27/1203
摘要： The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises: an SOI wafer comprising a semiconductor substrate, a buried insulation layer, and a semiconductor layer, wherein the buried insulation layer is disposed on the semiconductor substrate, and the semiconductor layer is disposed on the buried insulation layer; a plurality of MOSFETs being formed adjacently to each other in the SOI wafer, wherein each of the MOSFETs comprises a respective backgate being formed in the semiconductor substrate; and a plurality of shallow trench isolations, each of which being formed between respective adjacent MOSFETs to isolate the respective adjacent MOSFETs from each other, wherein the respective adjacent MOSFETs share a common backgate isolation region under and in direct contact with the respective backgate in the semiconductor substrate, and a PNP junction or an NPN junction is formed by the common backgate isolation region and the respective backgate of the respective adjacent MOSFETs. According to the present disclosure, respective backgates of two adjacent MOSFETs are isolated from each other by the shallow trench isolation. Furthermore, the two adjacent MOSFETs are also isolated from each other by the PNP or NPN junction formed by the respective backgates of the two adjacent MOSFETs and the common backgate isolation. As a result, this device structure has a better insulation effect over the prior art MOSFET and it greatly reduces the possibility of breakthrough.
摘要翻译：本发明提供一种半导体器件及其制造方法。半导体器件包括：SOI晶片，其包括半导体衬底，掩埋绝缘层和半导体层，其中所述掩埋绝缘层设置在所述半导体衬底上，并且所述半导体层设置在所述掩埋绝缘层上; 在SOI晶片中彼此相邻形成的多个MOSFET，其中每个MOSFET包括形成在半导体衬底中的相应后栅; 以及多个浅沟槽隔离，其中每一个均形成在各个相邻的MOSFET之间，以将各个相邻的MOSFET彼此隔离，其中相应的相邻MOSFET在半导体内部和相应的后栅极直接接触并与之直接接触。衬底，并且PNP结或NPN结由公共背栅隔离区和相应的相邻MOSFET的相应背栅形成。根据本公开，两个相邻MOSFET的相应背板通过浅沟槽隔离彼此隔离。此外，两个相邻的MOSFET也通过由两个相邻MOSFET的相应后沿和公共背栅隔离形成的PNP或NPN结彼此隔离。结果，该器件结构具有比现有技术的MOSFET更好的绝缘效果，并且大大降低了突破的可能性。

9. 发明授权

US08981454B2 Non-volatile memory device using finfet and method for manufacturing the same 有权
标题翻译：使用finfet的非易失性存储器件及其制造方法
公开(公告)号：US08981454B2
公开(公告)日：2015-03-17
申请号：US13061461
申请日：2010-09-25
申请人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L29/788 , H01L29/66 , H01L29/78
CPC分类号： H01L29/66825 , H01L21/28273 , H01L21/845 , H01L29/42324 , H01L29/785 , H01L29/7881
摘要： The present application discloses a non-volatile memory device, comprising a semiconductor fin on an insulating layer; a channel region at a central portion of the semiconductor fin; source/drain regions on both sides of the semiconductor fin; a floating gate arranged at a first side of the semiconductor fin and extending in a direction further away from the semiconductor fin; and a first control gate arranged on top of the floating gate or covering top and sidewall portions of the floating gate. The non-volatile memory device reduces a short channel effect, has an increased memory density, and is cost effective.
摘要翻译：本申请公开了一种非易失性存储器件，其包括绝缘层上的半导体鳍片; 在半导体鳍片的中心部分处的沟道区域; 半导体鳍片两侧的源极/漏极区域; 布置在半导体鳍片的第一侧并沿远离半导体鳍片的方向延伸的浮动栅极; 以及布置在所述浮动栅极的顶部上或覆盖所述浮动栅极的顶部和侧壁部分的第一控制栅极。非易失性存储器件减少短通道效应，具有增加的存储器密度，并且是成本有效的。

10. 发明授权

US08952453B2 MOSFET formed on an SOI wafer with a back gate 有权
标题翻译：在具有背栅的SOI晶片上形成MOSFET
公开(公告)号：US08952453B2
公开(公告)日：2015-02-10
申请号：US13580053
申请日：2011-11-18
申请人： Huilong Zhu , Qingqing Liang , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Qingqing Liang , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L27/12 , H01L21/84 , H01L29/66 , H01L29/786
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/66545 , H01L29/78648
摘要： The present application discloses a MOSFET and a method for manufacturing the same. The MOSFET is formed on an SOI wafer, comprising: a shallow trench isolation for defining an active region in the semiconductor layer; a gate stack on the semiconductor layer; a source region and a drain region in the semiconductor layer on both sides of the gate stack; a channel region in the semiconductor layer and sandwiched by the source region and the drain region; a back gate in the semiconductor substrate; a first dummy gate stack overlapping with a boundary between the semiconductor layer and the shallow trench isolation; and a second dummy gate stack on the shallow trench isolation, wherein the MOSFET further comprises a plurality of conductive vias which are disposed between the gate stack and the first dummy gate stack and electrically connected to the source region and the drain region respectively, and between the first dummy gate stack and the second dummy gate stack and electrically connected to the back gate. The MOSFET avoids short circuit between the back gate and the source/drain regions by the dummy gate stacks.
摘要翻译：本申请公开了一种MOSFET及其制造方法。 MOSFET形成在SOI晶片上，包括：用于限定半导体层中的有源区的浅沟槽隔离; 半导体层上的栅极堆叠; 栅极堆叠的两侧的半导体层中的源极区域和漏极区域; 半导体层中的沟道区，被源极区和漏极区夹持; 半导体衬底中的背栅; 与半导体层和浅沟槽隔离之间的边界重叠的第一虚拟栅极堆叠; 以及在浅沟槽隔离上的第二虚拟栅极堆叠，其中所述MOSFET还包括多个导电通孔，所述多个导电通孔设置在所述栅极堆叠和所述第一伪栅极堆叠之间，并分别电连接到所述源极区域和所述漏极区域之间，以及第一虚拟栅极堆叠和第二虚拟栅极堆叠并且电连接到背栅极。 MOSFET通过虚拟栅极堆叠避免了背栅极和源极/漏极区域之间的短路。

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