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    • 3. 发明授权
    • Semiconductor device
    • 半导体器件
    • US08037384B2
    • 2011-10-11
    • US12340549
    • 2008-12-19
    • Takumi HasegawaMotoyuki SatoTomoji NakamuraNobuo KonamiJun Matsushima
    • Takumi HasegawaMotoyuki SatoTomoji NakamuraNobuo KonamiJun Matsushima
    • G01R31/28
    • G01R31/318533
    • A semiconductor device includes a test target circuit; scan chains that enable scanning of the test target circuit; a first random number generation circuit that forms test patterns supplied to the scan chains; a second random number generation circuit that is provided separately from the first random number generation circuit; and a random number control circuit that uses the random numbers generated by the second random number generation circuit to change the random numbers generated by the first random number generation circuit. In a test of the semiconductor device, since a period of a clock of a scan chain does not need to be longer than that of a clock of a pattern generator, the number of clocks of the pattern generator needed for a test can be prevented from increasing. Accordingly, a test time can be prevented from increasing.
    • 半导体器件包括测试目标电路; 可扫描测试目标电路的扫描链; 形成提供给扫描链的测试图案的第一随机数生成电路; 与第一随机数生成电路分开设置的第二随机数生成电路; 以及使用由第二随机数生成电路产生的随机数来改变由第一随机数生成电路产生的随机数的随机数控制电路。 在半导体器件的测试中,由于扫描链的时钟周期不需要长于模式发生器的时钟周期,因此可以防止测试所需的模式发生器的时钟数 增加。 因此,可以防止测试时间增加。
    • 4. 发明授权
    • Test access control for plural processors of an integrated circuit
    • 集成电路的多个处理器的测试访问控制
    • US07743278B2
    • 2010-06-22
    • US11600208
    • 2006-11-16
    • Yuri IkedaYoshikazu AotoJun MatsushimaHiroyuki SasakiTomoyoshi UjiiMakoto Saen
    • Yuri IkedaYoshikazu AotoJun MatsushimaHiroyuki SasakiTomoyoshi UjiiMakoto Saen
    • G06F11/00
    • G01R31/31705G01R31/318572
    • The present invention is directed to facilitate debugging in a semiconductor integrated circuit device including a plurality of microprocessors. A semiconductor integrated circuit device includes: a plurality of processors; a plurality of debug interfaces enabling debugging of the corresponding processors; a plurality of common terminals shared by the plurality of debug interfaces; a selection circuit capable of selectively connecting the plurality of debug interfaces to the common terminals; and a controller capable of controlling selecting operation in the selection circuit in accordance with a predetermined instruction. A first selector capable of selectively connecting the plurality of debug interfaces to a TRST terminal in the terminal group conformed with the JTAG specifications, and a second selector capable of selectively connecting the plurality of debug interfaces to terminals other than the TRST terminal are provided. With the configuration, even in the case where the number of processors increases, the invention can flexibly address the increase.
    • 本发明旨在促进包括多个微处理器的半导体集成电路器件的调试。 半导体集成电路装置包括:多个处理器; 多个调试接口,能够调试相应的处理器; 由所述多个调试接口共享的多个公共终端; 选择电路,其能够将所述多个调试接口选择性地连接到所述公共端子; 以及控制器,其能够根据预定指令来控制选择电路中的选择操作。 提供能够选择性地将多个调试接口连接到符合JTAG规范的终端组中的TRST终端的第一选择器,并且提供能够选择性地将多个调试接口连接到除了TRST终端之外的终端的第二选择器。 利用该配置,即使在处理器数量增加的情况下,本发明可以灵活地解决增加的问题。
    • 8. 发明申请
    • SEMICONDUCTOR DEVICE
    • 半导体器件
    • US20090172488A1
    • 2009-07-02
    • US12340549
    • 2008-12-19
    • Takumi HasegawaMotoyuki SatoTomoji NakamuraNobuo KonamiJun Matsushima
    • Takumi HasegawaMotoyuki SatoTomoji NakamuraNobuo KonamiJun Matsushima
    • G01R31/3187
    • G01R31/318533
    • A semiconductor device includes a test target circuit; scan chains that enable scanning of the test target circuit; a first random number generation circuit that forms test patterns supplied to the scan chains; a second random number generation circuit that is provided separately from the first random number generation circuit; and a random number control circuit that uses the random numbers generated by the second random number generation circuit to change the random numbers generated by the first random number generation circuit. In a test of the semiconductor device, since a period of a clock of a scan chain does not need to be longer than that of a clock of a pattern generator, the number of clocks of the pattern generator needed for a test can be prevented from increasing. Accordingly, a test time can be prevented from increasing.
    • 半导体器件包括测试目标电路; 可扫描测试目标电路的扫描链; 形成提供给扫描链的测试图案的第一随机数生成电路; 与第一随机数生成电路分开设置的第二随机数生成电路; 以及使用由第二随机数生成电路产生的随机数来改变由第一随机数生成电路产生的随机数的随机数控制电路。 在半导体器件的测试中,由于扫描链的时钟周期不需要长于模式发生器的时钟周期,因此可以防止测试所需的模式发生器的时钟数 增加。 因此,可以防止测试时间增加。
    • 9. 发明授权
    • Image blur compensation device with reduced noise effect mechanism
    • 具有降低噪声影响机制的图像模糊补偿装置
    • US06574436B2
    • 2003-06-03
    • US08710108
    • 1996-09-12
    • Tadashi OtaniJun Matsushima
    • Tadashi OtaniJun Matsushima
    • G03B1700
    • H04N5/23258G03B2207/005G03B2217/005H04N5/23248H04N5/23287
    • An image blur compensation device including a mechanism that can effectively reduce the effects of noise which becomes a problem in image blur compensation devices which are used in still cameras, video cameras, and the like. Particularly, the noise becomes a problem during position detection using a position sensitive device. The image blur compensation device includes an image blur compensation optical system to compensate for image blur arising due to blurring motion of an optical device, a position detection unit to detect the position of the image blur compensation optical system, an image blur compensation drive unit to drive the image blur compensation optical system based on the detection result of the position detection unit, and a power supply circuit which performs power supply to the position detection unit and the image blur compensation drive unit by a switching step-up control. The image blur compensation device includes an inhibition device to inhibit the detection operation of the position detection unit in a fixed period in which the switching phase of the power supply circuit has changed.
    • 一种图像模糊补偿装置,包括能够有效地减少在静止照相机,摄像机等中使用的图像模糊补偿装置中成为问题的噪声的影响的机构。 特别地,在使用位置敏感装置的位置检测中噪声成为问题。 图像模糊补偿装置包括:图像模糊补偿光学系统,用于补偿由于光学装置的模糊运动引起的图像模糊;检测图像模糊补偿光学系统的位置的位置检测单元;图像模糊补偿驱动单元, 基于位置检测单元的检测结果驱动图像模糊补偿光学系统;以及电源电路,其通过切换升压控制向位置检测单元和图像模糊补偿驱动单元供电。 图像模糊补偿装置包括禁止装置,其在电源电路的开关相位已经改变的固定时段中禁止位置检测单元的检测操作。