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1. 发明申请

US20100308454A1 POWER SEMICONDUCTOR DEVICE PACKAGE AND FABRICATION METHOD 有权
标题翻译：功率半导体器件封装和制造方法
公开(公告)号：US20100308454A1
公开(公告)日：2010-12-09
申请号：US12479995
申请日：2009-06-08
申请人： Jun Lu , Francois Hebert , Kai Liu , Xiaotian Zhang
发明人： Jun Lu , Francois Hebert , Kai Liu , Xiaotian Zhang
IPC分类号： H01L23/48 , H01L21/78
CPC分类号： H01L23/492 , H01L23/04 , H01L24/37 , H01L24/40 , H01L25/072 , H01L29/0657 , H01L2224/37011 , H01L2224/40095 , H01L2224/40137 , H01L2224/40139 , H01L2224/73253 , H01L2224/84801 , H01L2224/8485 , H01L2224/97 , H01L2924/00014 , H01L2924/01006 , H01L2924/01015 , H01L2924/01027 , H01L2924/01033 , H01L2924/01074 , H01L2924/014 , H01L2924/12044 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/30105 , H01L2924/30107 , H01L2924/00 , H01L2224/83 , H01L2224/37099
摘要： A power semiconductor device package includes a conductive assembly including a connecting structure and a semiconductor die having an aperture formed therethrough, the aperture being sized and configured to spacedly receive the connecting structure. In an alternative embodiment, a power semiconductor device package includes a conductive assembly including a connecting structure and a pair of semiconductor die disposed on either side of the connecting structure in spaced relationship thereto.
摘要翻译：功率半导体器件封装包括导电组件，其包括连接结构和具有穿过其形成的孔的半导体管芯，所述孔的尺寸和构造为间隔地接收连接结构。在替代实施例中，功率半导体器件封装包括导电组件，该导电组件包括连接结构和设置在与之间隔开的连接结构的任一侧上的一对半导体管芯。

2. 发明申请

US20090057869A1 CO-PACKAGED HIGH-SIDE AND LOW-SIDE NMOSFETS FOR EFFICIENT DC-DC POWER CONVERSION 审中-公开
标题翻译：用于高效直流 - 直流电源转换的高压侧和低端NMOS管
公开(公告)号：US20090057869A1
公开(公告)日：2009-03-05
申请号：US11849160
申请日：2007-08-31
申请人： Francois Hebert , Xiaotian Zhang , Kai Liu , Ming Sun , Anup Bhalla
发明人： Francois Hebert , Xiaotian Zhang , Kai Liu , Ming Sun , Anup Bhalla
IPC分类号： H01L23/52
CPC分类号： H01L24/41 , H01L24/05 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/37 , H01L24/40 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/91 , H01L25/072 , H01L2224/0401 , H01L2224/04042 , H01L2224/05552 , H01L2224/05554 , H01L2224/0603 , H01L2224/16245 , H01L2224/32245 , H01L2224/37011 , H01L2224/40095 , H01L2224/40245 , H01L2224/40247 , H01L2224/4103 , H01L2224/45014 , H01L2224/45124 , H01L2224/48091 , H01L2224/48247 , H01L2224/48472 , H01L2224/4903 , H01L2224/49051 , H01L2224/49111 , H01L2224/49112 , H01L2224/49171 , H01L2224/73221 , H01L2224/73253 , H01L2224/73265 , H01L2224/83801 , H01L2224/85205 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01041 , H01L2924/01055 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/12032 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/3025 , H01L2924/00012 , H01L2924/00 , H01L2924/00015 , H01L2224/37099 , H01L2924/206
摘要： A circuit package assembly is disclosed. The assembly includes a conductive substrate; a high-side n-channel metal oxide semiconductor field effect transistor (NMOSFET) having a source on a side facing a surface of the conductive substrate and in electrical contact therewith and a low-side standard n-channel metal oxide semiconductor field effect transistor (NMOSFET) having a drain on a side facing the conductive substrate and in electrical contact therewith. Co-packaging of high-side and low-side NMOSFETs in this manner may reduce package size and parasitic inductance and capacitance compared to conventional packaging.
摘要翻译：公开了电路封装组件。组件包括导电基板; 具有在与导电基板的表面相对并与其电接触的一侧具有源极的高边n沟道金属氧化物半导体场效应晶体管（NMOSFET）和低侧标准n沟道金属氧化物半导体场效应晶体管（ NMOSFET），其在面向导电基板的一侧具有漏极并与其电接触。与传统封装相比，以这种方式共同封装高边和低边NMOSFET可以减小封装尺寸和寄生电感和电容。

3. 发明申请

US20090134964A1 Lead frame-based discrete power inductor 有权
标题翻译：引线框架分立功率电感
公开(公告)号：US20090134964A1
公开(公告)日：2009-05-28
申请号：US12011489
申请日：2008-01-25
申请人： Francois Hebert , Tao Feng , Xiaotian Zhang , Jun Lu
发明人： Francois Hebert , Tao Feng , Xiaotian Zhang , Jun Lu
IPC分类号： H01F5/00
CPC分类号： H01F17/062
摘要： A lead frame-based discrete power inductor is disclosed. The power inductor includes top and bottom lead frames, the leads of which form a coil around a single closed-loop magnetic core. The coil includes interconnections between inner and outer contact sections of the top and bottom lead frames, the magnetic core being sandwiched between the top and bottom lead frames. Ones of the leads of the top and bottom lead frames have a generally non-linear, stepped configuration such that the leads of the top lead frame couple adjacent leads of the bottom lead frame about the magnetic core to form the coil.
摘要翻译：公开了一种基于引线框架的分立功率电感器。功率电感器包括顶部和底部引线框架，其引线围绕单个闭环磁芯形成线圈。线圈包括顶部和底部引线框架的内部和外部接触部分之间的互连，磁芯夹在顶部和底部引线框架之间。顶部引线框架和底部引线框架的引线的一部分具有大致非线性的阶梯状构造，使得顶部引线框架的引线将底部引线框架的相邻引线围绕磁芯耦合以形成线圈。

4. 发明申请

US20090167477A1 Compact Inductive Power Electronics Package 有权
标题翻译：紧凑型感应电力电子封装
公开(公告)号：US20090167477A1
公开(公告)日：2009-07-02
申请号：US12397473
申请日：2009-03-04
申请人： Tao Feng , Xiaotian Zhang , Francois Hebert , Ming Sun
发明人： Tao Feng , Xiaotian Zhang , Francois Hebert , Ming Sun
IPC分类号： H01F5/00 , H01F41/00
CPC分类号： H01L23/495 , H01F3/14 , H01F17/0033 , H01F17/062 , H01F27/2828 , H01F2027/2814 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/16 , H01L2224/48091 , H01L2224/48465 , H01L2224/49175 , H01L2924/00014 , H01L2924/01019 , H01L2924/14 , H01L2924/181 , H01L2924/30107 , H01L2924/3025 , Y10T29/49073 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2924/00
摘要： An inductive power electronics package is disclosed. It has a circuit substrate with power inductor attached atop. The power inductor has inductor core of closed magnetic loop with an interior window. The closed magnetic loop can include air gap for inductance adjustment. The circuit substrate has bottom half-coil forming elements constituting a bottom half-coil beneath the inductor core. Also provided are top half-coil forming elements interconnected with the bottom half-coil forming elements to form an inductive coil enclosing the inductor core. An inner connection chip can be added in the interior window for interconnecting bottom half-coil forming elements with top half-coil forming elements. An outer connection chip can be added about the inductor core for interconnecting bottom half-coil forming elements with top half-coil forming elements outside the inductor core. A power Integrated Circuit can be attached to the top side of the circuit substrate as well.
摘要翻译：公开了感应电力电子封装。它有一个电路基板，带有功率电感器。功率电感器具有具有内部窗口的闭合磁环的电感器芯。封闭的磁环可以包括用于电感调节的气隙。电路基板具有构成电感器芯下方的下半线圈的底部半线圈形成元件。还提供了与底部半线圈形成元件互连以形成包围电感器芯的感应线圈的顶部半线圈形成元件。内部连接芯片可以添加到内部窗口中，用于将底部半线圈形成元件与顶部半线圈形成元件相互连接。外部连接芯片可以围绕电感器芯添加，用于将底部半线圈形成元件与电感器芯外部的顶部半线圈形成元件互连。功率集成电路也可以连接到电路基板的顶侧。

5. 发明申请

US20090134503A1 Semiconductor power device package having a lead frame-based integrated inductor 有权
标题翻译：具有引线框架的集成电感器的半导体功率器件封装
公开(公告)号：US20090134503A1
公开(公告)日：2009-05-28
申请号：US11986673
申请日：2007-11-23
申请人： Tao Feng , Xiaotian Zhang , Francois Hebert
发明人： Tao Feng , Xiaotian Zhang , Francois Hebert
IPC分类号： H01L23/495 , H01L21/60
CPC分类号： H01L23/495 , H01F17/0033 , H01F2027/2814 , H01L24/48 , H01L24/49 , H01L2224/05553 , H01L2224/05554 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/49171 , H01L2924/00014 , H01L2924/01006 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01082 , H01L2924/014 , H01L2924/10161 , H01L2924/14 , H01L2924/1461 , H01L2924/181 , H01L2924/19107 , H01L2924/30107 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： A semiconductor power device package having a lead frame-based integrated inductor is disclosed. The semiconductor power device package includes a lead frame having a plurality of leads, a inductor core attached to the lead frame such that a plurality of lead ends are exposed through a window formed in the inductor core, a plurality of bonding wires, ones of the plurality of bonding wires coupling each of the plurality of lead ends to adjacent leads about the inductor core to form the inductor, and a power integrated circuit coupled to the inductor. In alternative embodiments, a top lead frame couples each of the plurality of lead ends to adjacent leads about the inductor core by means of a connection chip.
摘要翻译：公开了一种具有引线框架的集成电感器的半导体功率器件封装。半导体功率器件封装包括具有多个引线的引线框架，附接到引线框架的电感器芯，使得多个引线端通过形成在电感器芯中的窗体露出，多个接合线，多个接合线将多个引线端中的每一个连接到围绕电感器芯的相邻引线以形成电感器，以及耦合到电感器的功率集成电路。在替代实施例中，顶部引线框架通过连接芯片将多个引线端中的每一个耦合到围绕电感器芯的相邻引线。

6. 发明申请

US20100133670A1 Top-side Cooled Semiconductor Package with Stacked Interconnection Plates and Method 有权
标题翻译：顶部冷却半导体封装与堆叠互连板和方法
公开(公告)号：US20100133670A1
公开(公告)日：2010-06-03
申请号：US12326065
申请日：2008-12-01
申请人： Kai Liu , Francois Hebert , Lei Shi
发明人： Kai Liu , Francois Hebert , Lei Shi
IPC分类号： H01L23/495 , H01L21/60
CPC分类号： H01L21/56 , H01L21/50 , H01L23/49524 , H01L23/49562 , H01L23/49568 , H01L24/36 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/48 , H01L2224/32245 , H01L2224/37011 , H01L2224/40095 , H01L2224/40245 , H01L2224/40247 , H01L2224/40249 , H01L2224/4103 , H01L2224/48247 , H01L2224/73263 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01027 , H01L2924/01033 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/10329 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/30107 , H01L2924/3011 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2224/37099
摘要： A top-side cooled semiconductor package with stacked interconnection plate is disclosed. The semiconductor package includes a circuit substrate with terminal leads, a semiconductor die atop the circuit substrate, a low thermal resistance intimate interconnection plate for bonding and interconnecting a top contact area of the semiconductor die with the circuit substrate, a low thermal resistance stacked interconnection plate atop the intimate interconnection plate for top-side cooling, a molding encapsulant for encapsulating the package except for exposing a top surface of the stacked interconnection plate to maintain effective top-side cooling. The top portion of the stacked interconnection plate can include a peripheral overhang above the intimate interconnection plate. The peripheral overhang allows for a maximized exposed top surface area for heat dissipation independent of otherwise areal constraints applicable to the intimate interconnection plate. The stacked interconnection plate can be partially etched or three dimensionally formed to create the peripheral overhang.
摘要翻译：公开了一种具有堆叠互连板的顶侧冷却半导体封装。半导体封装包括具有端子引线的电路基板，电路基板顶部的半导体管芯，用于将半导体管芯的顶部接触区域与电路基板接合和互连的低热电阻紧密互连板，低热阻堆叠互连板位于用于顶侧冷却的紧密互连板顶部，用于封装包装的模制密封剂，除了暴露堆叠的互连板的顶表面以保持有效的顶侧冷却。堆叠的互连板的顶部可以包括在紧密互连板上方的周边突出部。外围悬垂允许最大化的暴露的顶部表面积用于散热，而不管适用于紧密互连板的其它面积约束。层叠的互连板可以被部分蚀刻或三维地形成以产生外围悬垂。

7. 发明申请

US20100133674A1 Compact Semiconductor Package with Integrated Bypass Capacitor and Method 有权
标题翻译：具有集成旁路电容器和方法的紧凑型半导体封装
公开(公告)号：US20100133674A1
公开(公告)日：2010-06-03
申请号：US12330381
申请日：2008-12-08
申请人： Francois Hebert , Kai Liu
发明人： Francois Hebert , Kai Liu
IPC分类号： H01L23/538 , H01L21/62
CPC分类号： H01L23/49524 , H01L23/49562 , H01L23/49575 , H01L23/49589 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/48 , H01L2224/37011 , H01L2224/40095 , H01L2224/40245 , H01L2224/40247 , H01L2224/48247 , H01L2224/48465 , H01L2224/73221 , H01L2224/73265 , H01L2224/83801 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/10329 , H01L2924/13055 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/30107 , H01L2924/3011 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2224/37099 , H01L2224/84
摘要： A top-side cooled compact semiconductor package with integrated bypass capacitor is disclosed. The top-side cooled compact semiconductor package includes a circuit substrate with terminal leads, numerous semiconductor dies bonded atop the circuit substrate, numerous elevation-adaptive interconnection plates for bonding and interconnecting top contact areas of the semiconductor dies with the circuit substrate, a first member of the elevation-adaptive interconnection plates has a first flat-top area and a second member of the elevation-adaptive interconnection plates has a second flat-top area in level with the first flat-top area, a bypass capacitor, having two capacitor terminals located at its ends, stacked atop the two interconnection plate members while being bonded thereto via the first flat-top area and the second flat-top area for a reduced interconnection parasitic impedance.
摘要翻译：公开了具有集成旁路电容器的顶侧冷却紧凑型半导体封装。顶侧冷却的紧凑型半导体封装包括具有端子引线的电路基板，接合在电路基板顶上的多个半导体管芯，用于将半导体管芯的顶部接触区域与电路基板接合和互连的许多仰角自适应互连板，第一构件所述高度自适应互连板具有第一平顶区域，并且所述仰角自适应互连板的第二构件具有与所述第一平顶区域平齐的第二平顶区域，具有两个电容器端子的旁路电容器位于其端部，并且通过第一平顶部区域和第二平顶部区域结合到两个互连板构件的顶部，以减少互连寄生阻抗。

8. 发明申请

US20090108456A1 Solder-top Enhanced Semiconductor Device and Method for Low Parasitic Impedance Packaging 有权
标题翻译：焊接增强型半导体器件和低寄生阻抗封装方法
公开(公告)号：US20090108456A1
公开(公告)日：2009-04-30
申请号：US11932845
申请日：2007-10-31
申请人： Francois Hebert , Anup Bhalla , Kai Liu , Ming Sun
发明人： Francois Hebert , Anup Bhalla , Kai Liu , Ming Sun
IPC分类号： H01L23/488 , H01L21/60
CPC分类号： H01L24/40 , H01L23/4952 , H01L23/49562 , H01L23/64 , H01L24/29 , H01L24/33 , H01L24/37 , H01L24/41 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/83 , H01L2224/05624 , H01L2224/29101 , H01L2224/29111 , H01L2224/32245 , H01L2224/37011 , H01L2224/40095 , H01L2224/40245 , H01L2224/40247 , H01L2224/40249 , H01L2224/4103 , H01L2224/45014 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/48472 , H01L2224/48624 , H01L2224/48724 , H01L2224/48824 , H01L2224/4903 , H01L2224/49051 , H01L2224/49111 , H01L2224/49171 , H01L2224/83194 , H01L2224/83801 , H01L2224/84801 , H01L2924/0001 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01067 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/0133 , H01L2924/014 , H01L2924/13091 , H01L2924/14 , H01L2924/157 , H01L2924/181 , H01L2924/19043 , H01L2924/20752 , H01L2924/20753 , H01L2924/20754 , H01L2924/20755 , H01L2924/20756 , H01L2924/20757 , H01L2924/20758 , H01L2924/20759 , H01L2924/2076 , H01L2924/30107 , H01L2924/3011 , H01L2924/00 , H01L2924/00012 , H01L2224/29099 , H01L2224/37099
摘要： A solder-top enhanced semiconductor device is proposed for packaging. The solder-top device includes a device die with a top metal layer patterned into contact zones and contact enhancement zones. At least one contact zone is electrically connected to at least one contact enhancement zone. Atop each contact enhancement zone is a solder layer for an increased composite thickness thus lowered parasitic impedance. Where the top metal material can not form a uniform good electrical bond with the solder material, the device die further includes an intermediary layer sandwiched between and forming a uniform electrical bond with the top metal layer and the solder layer. A method for making the solder-top device includes: a) Lithographically patterning the top metal layer into the contact zones and the contact enhancement zones. b) Forming a solder layer atop each of the contact enhancement zones using a stencil process for an increased composite thickness.
摘要翻译：提出了一种焊顶增强型半导体器件进行封装。焊料顶部器件包括具有图案化为接触区域和接触增强区域的顶部金属层的器件裸片。至少一个接触区域电连接到至少一个接触增强区域。每个接触增强区顶部都是一个焊料层，用于增加复合材料厚度，从而降低寄生阻抗。在顶部金属材料不能与焊料材料形成均匀的良好电接合的情况下，器件裸片还包括夹在中间层之间并与顶部金属层和焊料层形成均匀的电接合的中间层。用于制造焊料顶部器件的方法包括：a）将顶部金属层的光刻图案化成接触区域和接触增强区域。 b）使用用于增加复合材料厚度的模版工艺在每个接触增强区的顶部上形成焊料层。

9. 发明申请

US20110107589A1 PLANAR GROOVED POWER INDUCTOR STRUCTURE AND METHOD 有权
标题翻译：平面电力电力电感器结构与方法
公开(公告)号：US20110107589A1
公开(公告)日：2011-05-12
申请号：US13007551
申请日：2011-01-14
申请人： Francois Hebert , Tao Feng , Jun Lu
发明人： Francois Hebert , Tao Feng , Jun Lu
IPC分类号： H01F7/06
CPC分类号： H01F17/0033 , H01F1/344 , H01F41/046 , H01F2017/002 , Y10T29/4902
摘要： An inductor may include a planar ferrite core. A first group of one or more grooves is formed in a first side of the ferrite core. A second group of two or more grooves is formed in a second side of the ferrite core. The grooves in the first and second groups are oriented such that each groove in the first group overlaps with two corresponding grooves in the second group. A first plurality of vias communicates through the ferrite core between the first and second sides of the ferrite core. Each via is located where a groove in the first group overlaps with a groove in the second group. A conductive material is disposed in the first and second groups of grooves and in the vias to form an inductor coil.
摘要翻译：电感器可以包括平面铁氧体磁芯。第一组一个或多个凹槽形成在铁氧体磁芯的第一侧。在铁氧体磁芯的第二侧形成有第二组两个或多个凹槽。第一组和第二组中的凹槽被定向成使得第一组中的每个凹槽与第二组中的两个相应的凹槽重叠。第一多个通孔在铁氧体磁芯的第一和第二侧之间通过铁氧体磁芯连通。每个通孔位于第一组中的凹槽与第二组中的凹槽重叠的位置。导电材料设置在第一和第二组沟槽和通孔中以形成电感线圈。

10. 发明申请

US20090322461A1 PLANAR GROOVED POWER INDUCTOR STRUCTURE AND METHOD 有权
标题翻译：平面电力电力电感器结构与方法
公开(公告)号：US20090322461A1
公开(公告)日：2009-12-31
申请号：US12165423
申请日：2008-06-30
申请人： Francois Hebert , Tao Feng , Jun Lu
发明人： Francois Hebert , Tao Feng , Jun Lu
IPC分类号： H01F27/02
CPC分类号： H01F17/0033 , H01F1/344 , H01F41/046 , H01F2017/002 , Y10T29/4902
摘要： An inductor may include a planar ferrite core. A first group of one or more grooves is formed in a first side of the ferrite core. A second group of two or more grooves is formed in a second side of the ferrite core. The grooves in the first and second groups are oriented such that each groove in the first group overlaps with two corresponding grooves in the second group. A first plurality of vias communicates through the ferrite core between the first and second sides of the ferrite core. Each via is located where a groove in the first group overlaps with a groove in the second group. A conductive material is disposed in the first and second groups of grooves and in the vias to form an inductor coil.
摘要翻译：电感器可以包括平面铁氧体磁芯。第一组一个或多个凹槽形成在铁氧体磁芯的第一侧。在铁氧体磁芯的第二侧形成有第二组两个或多个凹槽。第一组和第二组中的凹槽被定向成使得第一组中的每个凹槽与第二组中的两个相应的凹槽重叠。第一多个通孔在铁氧体磁芯的第一和第二侧之间通过铁氧体磁芯连通。每个通孔位于第一组中的凹槽与第二组中的凹槽重叠的位置。导电材料设置在第一和第二组沟槽和通孔中以形成电感线圈。

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