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1. 发明授权

US07169670B2 Method of forming gate oxide layer in semiconductor device 失效
标题翻译：在半导体器件中形成栅氧化层的方法
公开(公告)号：US07169670B2
公开(公告)日：2007-01-30
申请号：US10880691
申请日：2004-06-30
申请人： Min Kyu Lee , Hee Hyun Chang , Jum Soo Kim , Jung Ryul Ahn
发明人： Min Kyu Lee , Hee Hyun Chang , Jum Soo Kim , Jung Ryul Ahn
IPC分类号： H01L21/336
CPC分类号： H01L27/11526 , H01L21/823462 , H01L27/105 , H01L27/11534 , Y10S438/981
摘要： Provided is related to a method of forming a semiconductor device comprises steps of: providing a semiconductor substrate having a low voltage region and a high voltage region; forming a pad oxide layer and a pad nitride layer in sequence on the semiconductor substrate; removing the pad nitride layer and the pad oxide layer on the semiconductor substrate of the high voltage region, wherein a surface of the semiconductor substrate of the high voltage region is exposed and recessed; forming a sacrificial oxide layer on the surface of the semiconductor substrate of the high voltage region; removing the sacrificial layer; forming a first gate oxide layer on the surface of the semiconductor substrate of the high voltage region; removing the pad oxide layer and the pad nitride layer left on the semiconductor substrate of the low voltage region, wherein a surface of the semiconductor substrate of the low voltage region is exposed and recessed; and forming a second gate oxide layer on the first gate oxide layer and the surface of the semiconductor substrate of the low voltage region.
摘要翻译：提供一种形成半导体器件的方法，包括以下步骤：提供具有低电压区域和高电压区域的半导体衬底; 在半导体衬底上依次形成焊盘氧化物层和焊盘氮化物层; 去除高电压区域的半导体衬底上的衬垫氮化物层和衬垫氧化物层，其中高压区域的半导体衬底的表面被暴露和凹陷; 在高电压区域的半导体衬底的表面上形成牺牲氧化物层; 去除牺牲层; 在所述高电压区域的半导体衬底的表面上形成第一栅氧化层; 去除低电压区域的半导体衬底上留下的衬垫氧化物层和衬垫氮化物层，其中低电压区域的半导体衬底的表面露出并凹陷; 以及在所述第一栅极氧化物层和所述低电压区域的所述半导体衬底的表面上形成第二栅极氧化物层。

2. 发明授权

US08520440B2 Semiconductor memory device and method of operating the same 有权
标题翻译：半导体存储器件及其操作方法
公开(公告)号：US08520440B2
公开(公告)日：2013-08-27
申请号：US13297467
申请日：2011-11-16
申请人： Jung Ryul Ahn , Sang Hyun Oh , Jum Soo Kim
发明人： Jung Ryul Ahn , Sang Hyun Oh , Jum Soo Kim
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/16 , H01L27/11524
摘要： A method of operating a semiconductor memory device includes a memory array having memory cell strings including a first and a second memory cell groups having memory cells, a first and a second dummy elements, a drain select transistor and a source select transistor, wherein the first memory cell group and the second memory cell group are arranged between the drain select transistor and the source select transistor; connecting electrically the first memory cell group to the second memory cell group during a program operation or a read operation of the first memory cell group or the second memory cell group; and performing separately an erase operation of the first memory cell group and an erase operation of the second memory cell group, selecting simultaneously one of the first dummy element and the second dummy element during the erase operation of the selected memory cell group.
摘要翻译：一种操作半导体存储器件的方法包括具有存储单元串的存储器阵列，存储单元串包括具有存储单元的第一和第二存储单元组，第一和第二虚设元件，漏极选择晶体管和源选择晶体管，其中第一存储单元组和第二存储单元组布置在漏极选择晶体管和源极选择晶体管之间; 在第一存储单元组或第二存储单元组的编程操作或读操作期间将第一存储单元组电连接到第二存储单元组; 以及分别执行第一存储单元组的擦除操作和第二存储单元组的擦除操作，在所选存储单元组的擦除操作期间同时选择第一虚拟元件和第二虚设元件中的一个。

3. 发明授权

US07041555B2 Method for manufacturing flash memory device 有权
标题翻译：闪存器件制造方法
公开(公告)号：US07041555B2
公开(公告)日：2006-05-09
申请号：US10883279
申请日：2004-06-30
申请人： Jung Ryul Ahn , Jum Soo Kim
发明人： Jung Ryul Ahn , Jum Soo Kim
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524
摘要： Disclosed is a method for manufacturing a flash memory device. In a process of forming a flash memory cell and a select transistor through a process of forming a polysilicon layer for a floating gate, a process of forming a dielectric layer and a process of forming a polysilicon layer for a control gate, the dielectric layer is formed and the dielectric layer in a region where a select transistor will be formed is then removed, thereby forming a select gate line in which the polysilicon layer for the floating gate and the polysilicon layer for the control gate are electrically connected. Furthermore, in a process of forming a flash memory cell and a select transistor through a process of forming a polysilicon layer for a floating gate, a process of forming a dielectric layer and a process of forming a polysilicon layer for a control gate, forming an interlayer insulating layer on the entire structure and then forming a contact, the dielectric layer on the polysilicon layer for the floating gate in a region where a select transistor will be formed and the polysilicon layer for the control gate are all removed whereby the polysilicon layer for the floating gate and a contact plug are directly electrically connected.
摘要翻译：公开了一种用于制造闪速存储器件的方法。在通过形成用于浮置栅极的多晶硅层的工艺，形成介电层的工艺和形成用于控制栅极的多晶硅层的工艺来形成闪存单元和选择晶体管的过程中，介电层是然后去除形成选择晶体管的区域中的电介质层，从而形成选择栅极线，其中浮栅的多晶硅层和用于控制栅的多晶硅层电连接。此外，在通过形成用于浮置栅极的多晶硅层的工艺来形成闪存单元和选择晶体管的过程中，形成介电层的工艺和形成用于控制栅极的多晶硅层的工艺，形成层间绝缘层，然后形成接触，在形成选择晶体管的区域中的浮栅的多晶硅层上的电介质层和用于控制栅极的多晶硅层全部被去除，由此用于浮动栅极和接触插头直接电连接。

4. 发明申请

US20070155124A1 Method of manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20070155124A1
公开(公告)日：2007-07-05
申请号：US11593868
申请日：2006-11-07
申请人： Jung Ryul Ahn , Jum Soo Kim
发明人： Jung Ryul Ahn , Jum Soo Kim
IPC分类号： H01L21/76
CPC分类号： H01L21/76229 , H01L27/1052
摘要： A method of manufacturing a semiconductor device wherein a gate insulating layer and a polysilicon layer are formed over a semiconductor substrate in which a cell region and a peri region are defined. Portions of the polysilicon layer, the gate insulating layer, and the semiconductor substrate of the peri region are etched to form a first trench in the peri region. A first insulating layer is formed on the entire surface so that the first trench is gap filled. Portions of the first insulating layer, the first polysilicon layer, the gate insulating layer, and the semiconductor substrate of the cell region are etched to form second trenches in the cell region. A sidewall oxide layer and a nitride layer are formed within the second trenches, so that the sidewall oxide layer and the nitride layer are laminated. The second trenches are gap-filled with a second insulating layer to form isolation layers. Since plasma attack and the infiltration of hydrogen (H2) can be prevented, the malfunction of a cell and peripheral circuits can be prevented.
摘要翻译：一种半导体器件的制造方法，其中在限定了单元区域和周边区域的半导体衬底上形成栅极绝缘层和多晶硅层。蚀刻多晶硅层的一部分，栅极绝缘层和半导体衬底，以在周边区域形成第一沟槽。在整个表面上形成第一绝缘层，使得第一沟槽间隙填充。蚀刻单元区域的第一绝缘层，第一多晶硅层，栅极绝缘层和半导体衬底的部分，以在单元区域中形成第二沟槽。在第二沟槽内形成侧壁氧化物层和氮化物层，从而层叠侧壁氧化物层和氮化物层。第二沟槽间隙填充有第二绝缘层以形成隔离层。由于可以防止等离子体侵蚀和氢（H 2 2）的渗透，所以可以防止电池和外围电路的故障。

5. 发明授权

US07015099B2 Method of manufacturing a flash memory cell capable of increasing a coupling ratio 失效
标题翻译：制造能够提高耦合比的闪存单元的方法
公开(公告)号：US07015099B2
公开(公告)日：2006-03-21
申请号：US11004301
申请日：2004-12-03
申请人： Jum Soo Kim , Sung Mun Jung , Jung Ryul Ahn , Young Ki Shin , Young Bok Lee
发明人： Jum Soo Kim , Sung Mun Jung , Jung Ryul Ahn , Young Ki Shin , Young Bok Lee
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L21/76235
摘要： A method of manufacturing a flash memory cell. The method includes controlling a wall sacrificial oxidization process, a wall oxidization process and a cleaning process of a trench insulating film that are performed before/after a process of forming the trench insulating film for burying a trench to etch the trench insulating film to a desired space. Therefore, it is possible to secure the coupling ratio of a floating gate by maximum and implement a device of a smaller size.
摘要翻译：一种制造闪存单元的方法。该方法包括控制在形成用于埋入沟槽的沟槽绝缘膜的工艺之前/之后执行的沟槽绝缘膜的壁牺牲氧化过程，壁氧化过程和清洁过程，以将沟槽绝缘膜蚀刻到期望的空间。因此，可以最大限度地确保浮动栅极的耦合比，并且实现更小尺寸的器件。

6. 发明授权

US08937344B2 Semiconductor device and method of manufacturing the same 有权
公开(公告)号：US08937344B2
公开(公告)日：2015-01-20
申请号：US13596393
申请日：2012-08-28
申请人： Jung Ryul Ahn , Jum Soo Kim
发明人： Jung Ryul Ahn , Jum Soo Kim
IPC分类号： H01L27/108 , H01L27/105 , H01L27/115 , H01L49/02
CPC分类号： H01L28/60 , H01L21/76224 , H01L21/76897 , H01L27/105 , H01L27/1052 , H01L27/11529 , H01L28/90
摘要： The semiconductor device includes a semiconductor substrate having a cell region and a peripheral circuit region defined therein, semiconductor memory elements formed over the semiconductor substrate in the cell region, an interlayer insulating layer formed over the semiconductor substrate in the peripheral circuit region, first conductive layers substantially vertically passing through the interlayer insulating layer, and arranged in a matrix, and second conductive layers coupling the first conductive layers in rows or columns, each pair of the second conductive layers and the first conductive layers coupled to the each pair of the second conductive layers, respectively, forming electrodes of a capacitor.

7. 发明授权

US07696074B2 Method of manufacturing NAND flash memory device 失效
标题翻译：制造NAND闪存器件的方法
公开(公告)号：US07696074B2
公开(公告)日：2010-04-13
申请号：US11446475
申请日：2006-06-02
申请人： Jum Soo Kim , Jung Ryul Ahn
发明人： Jum Soo Kim , Jung Ryul Ahn
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L27/11524 , H01L21/76897 , H01L27/115 , H01L27/11521
摘要： A method of manufacturing a NAND flash memory device, including the steps of forming gates over a semiconductor substrate; forming a junction region over the semiconductor substrate between the gates; forming a buffer oxide film on the gates and the semiconductor substrate; stripping the buffer oxide film at one side of the gates; forming a nitride film spacers over the sidewalls of the gates; forming a self-aligned contact process (SAC) nitride film and an insulating film over the entire structure; etching regions of the insulating film and the SAC nitride film to form a contact through which the junction region is exposed; and forming a conductive film to bury the contact, thereby forming a contact plug.
摘要翻译：一种制造NAND闪存器件的方法，包括在半导体衬底上形成栅极的步骤; 在所述栅极之间的所述半导体衬底上形成结区; 在栅极和半导体衬底上形成缓冲氧化膜; 剥离栅极一侧的缓冲氧化膜; 在栅极的侧壁上形成氮化物膜间隔物; 在整个结构上形成自对准接触工艺（SAC）氮化物膜和绝缘膜; 蚀刻绝缘膜和SAC氮化物膜的区域，以形成接合区域暴露的触点; 并形成导电膜以埋置接触，从而形成接触塞。

8. 发明授权

US07465631B2 Method of fabricating a non-volatile memory device 有权
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US07465631B2
公开(公告)日：2008-12-16
申请号：US11634622
申请日：2006-12-06
申请人： Jung Ryul Ahn , Jum Soo Kim
发明人： Jung Ryul Ahn , Jum Soo Kim
IPC分类号： H01L21/336
CPC分类号： H01L29/42324
摘要： A non-volatile memory device and a method of manufacturing the same, in which the program speed can be enhanced and the interference phenomenon can be reduced. The non-volatile memory device includes a semiconductor substrate having an active region defined by isolation layers arranged in one direction, a control gate arranged vertically to the direction in which the isolation layers are arranged, a floating gate formed on the active region below the control gate and having a lateral curve so that the floating gate has a width narrowed upwardly, a gate insulating layer formed between the floating gate and the semiconductor substrate, and a dielectric layer formed between the floating gate and the control gate.
摘要翻译：一种非易失性存储器件及其制造方法，其中可以提高程序速度并且可以减少干扰现象。非易失性存储器件包括：半导体衬底，其具有由沿一个方向布置的隔离层限定的有源区;垂直于隔离层布置方向布置的控制栅;形成在控制下方的有源区上的浮置栅并且具有横向曲线，使得浮动栅极具有向上变窄的宽度，形成在浮置栅极和半导体衬底之间的栅极绝缘层，以及形成在浮动栅极和控制栅极之间的介电层。

9. 发明申请

US20070235800A1 Non-volatile memory device and method of manufacturing the same 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20070235800A1
公开(公告)日：2007-10-11
申请号：US11634622
申请日：2006-12-06
申请人： Jung Ryul Ahn , Jum Soo Kim
发明人： Jung Ryul Ahn , Jum Soo Kim
IPC分类号： H01L29/788
CPC分类号： H01L29/42324
摘要： A non-volatile memory device and a method of manufacturing the same, in which the program speed can be enhanced and the interference phenomenon can be reduced. The non-volatile memory device includes a semiconductor substrate having an active region defined by isolation layers arranged in one direction, a control gate arranged vertically to the direction in which the isolation layers are arranged, a floating gate formed on the active region below the control gate and having a lateral curve so that the floating gate has a width narrowed upwardly, a gate insulating layer formed between the floating gate and the semiconductor substrate, and a dielectric layer formed between the floating gate and the control gate.
摘要翻译：一种非易失性存储器件及其制造方法，其中可以提高程序速度并且可以减少干扰现象。非易失性存储器件包括：半导体衬底，其具有由沿一个方向布置的隔离层限定的有源区;垂直于隔离层布置方向布置的控制栅;形成在控制下方的有源区上的浮置栅并且具有横向曲线，使得浮动栅极具有向上变窄的宽度，形成在浮置栅极和半导体衬底之间的栅极绝缘层，以及形成在浮动栅极和控制栅极之间的介电层。

10. 发明授权

US07049236B2 Method of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07049236B2
公开(公告)日：2006-05-23
申请号：US10623341
申请日：2003-07-18
申请人： Jum Soo Kim , Jung Ryul Ahn
发明人： Jum Soo Kim , Jung Ryul Ahn
IPC分类号： H01L21/302
CPC分类号： H01L27/11521 , H01L21/28273
摘要： Disclosed is a method of manufacturing a semiconductor device. A gate electrode, which was formed through existing mask and etch processes, is formed by forming an oxide film protrusion on a field oxide film and forming the gate electrode between the oxide film protrusions. It is thus possible to minimize the critical dimension of the device, easily adjust the size of the device and form a uniform gate electrode over the wafer.
摘要翻译：公开了半导体器件的制造方法。通过现有掩模和蚀刻工艺形成的栅极通过在场氧化膜上形成氧化膜突起并在氧化物膜突起之间形成栅电极而形成。因此可以使器件的临界尺寸最小化，容易地调节器件的尺寸并在晶片上形成均匀的栅电极。

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