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1. 发明授权

US06594184B2 System and method for accessing a memory array which tolerates non-exclusive read select enables 有权
标题翻译：用于访问允许非排他读取选择的存储器阵列的系统和方法使能
公开(公告)号：US06594184B2
公开(公告)日：2003-07-15
申请号：US09948180
申请日：2001-09-06
申请人： Julie M. Staraitis , Marc E. Lamere , Jason Eisenberg , Micah C. Knapp
发明人： Julie M. Staraitis , Marc E. Lamere , Jason Eisenberg , Micah C. Knapp
IPC分类号： G11C700
CPC分类号： G11C8/12 , G11C8/10
摘要： A memory array includes a plurality of memory cells logically arranged in M rows and N columns, wherein N is the number of memory cells per word of digital information and M is the number of words within the array. A plurality of N data output lines are associated with each of the N columns of the array for selectively retrieving output data from a word located at a predetermined word address in the array. Each data output line is selectively shared by each of the M memory cells within its associated column. Each of the cell output lines of the M memory cells in each of the N columns are logically OR-ed together to provide the output data retrieved by each data output line associated with each of the N columns.
摘要翻译：存储器阵列包括逻辑上排列成M行和N列的多个存储器单元，其中N是数字信息每个字的存储器单元的数量，M是阵列内的字数。多个N个数据输出线与阵列的N列中的每一个相关联，用于从位于阵列中的预定字地址的字选择性地检索输出数据。每个数据输出线由其相关联的列中的每个M个存储器单元选择性共享。 N列中的每一个中的M个存储器单元的单元输出行的每个单元输出行一起被逻辑或并行，以提供与每个N列相关联的每个数据输出行检索的输出数据。

2. 发明授权

US06587369B2 Two-stage memory cell 有权
公开(公告)号：US06587369B2
公开(公告)日：2003-07-01
申请号：US09852429
申请日：2001-05-09
申请人： Julie M. Staraitis , Spencer Gold , Jason Eisenberg
发明人： Julie M. Staraitis , Spencer Gold , Jason Eisenberg
IPC分类号： G11C1100
CPC分类号： G11C15/04 , G11C8/16
摘要： A memory cell is provided to store a speculative data value until either a later speculative data value is generated or until the stored speculative data is determined to be the desired data, e.g. no longer speculative. At such time, the invention allows the stored speculative data to quickly and easily be stored as permanent data and further speculative data values to be stored.

3. 发明授权

US07055020B2 Flushable free register list having selected pointers moving in unison 有权
标题翻译：具有选择的一致移动的指针的可刷新的自由寄存器列表
公开(公告)号：US07055020B2
公开(公告)日：2006-05-30
申请号：US09881071
申请日：2001-06-13
申请人： Spencer M. Gold , Julie M. Staraitis , Jason Eisenberg
发明人： Spencer M. Gold , Julie M. Staraitis , Jason Eisenberg
IPC分类号： G06F9/50
CPC分类号： G06F9/3851 , G06F9/3842
摘要： A method and apparatus is provided for restoring a free physical register list to its previous state without having to physically restore any data. The method and semiconductor device utilizes sets of pointers to manage physical register pointers in the physical register list. The physical register list is able to independently track physical registers for multiple threads of a multithreading microprocessor.
摘要翻译：提供了一种方法和装置，用于将空闲物理寄存器列表恢复到其先前状态，而不必物理地恢复任何数据。该方法和半导体器件利用指针集来管理物理寄存器列表中的物理寄存器指针。物理寄存器列表能够独立地跟踪多线程微处理器的多个线程的物理寄存器。

4. 发明授权

US06711664B1 Method and system for decoding a row address to assert multiple adjacent rows in a memory structure 有权
标题翻译：用于解码行地址以在存储器结构中断言多个相邻行的方法和系统
公开(公告)号：US06711664B1
公开(公告)日：2004-03-23
申请号：US09660721
申请日：2000-09-13
申请人： Spencer M. Gold , Jason Eisenberg
发明人： Spencer M. Gold , Jason Eisenberg
IPC分类号： G06F1200
CPC分类号： G11C8/12
摘要： A memory array or structure and method for decoding a read address to facilitate simultaneous reading of successive rows. The memory includes row decoders in the form of decoding logic for enabling multiple rows of the memory structure to be read in response to a single row address. The memory structure helps to reduce the number of ports that are required for the memory structure and, thus, reduces the die area occupied by the memory structure. The row address may be divided into most significant bits and least significant bits. Further, the decoding logic may decode the most significant bits differently from the least significant bits when processing the row address. The most significant bits may be preprocessed or predecoded into a fully decoded format while the least significant bits may be decoded into a priority decoded format.
摘要翻译：一种用于对读取地址进行解码以便于同时读取连续行的存储器阵列或结构和方法。存储器包括解码逻辑形式的行解码器，用于响应于单个行地址来读取存储器结构的多行。存储器结构有助于减少存储器结构所需的端口数量，从而减少存储器结构占用的管芯面积。行地址可以被分成最高有效位和最低有效位。此外，当处理行地址时，解码逻辑可以与最低有效位不同地解码最高有效位。最高有效位可以被预处理或预解码成完全解码格式，而最低有效位可被解码为优先解码格式。

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