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    • 1. 发明授权
    • Method for designing masks used to form electronic components
    • 用于形成用于形成电子部件的掩模的方法
    • US08413082B2
    • 2013-04-02
    • US13117164
    • 2011-05-27
    • Julia Castellan
    • Julia Castellan
    • G06F17/50G06F19/00G03F1/00G21K5/00
    • G06F17/5081G06F2217/12Y02P90/265
    • A method for designing masks adapted to the forming of integrated circuits, including the steps of: (a) forming a first test file including a set of configurations of integrated circuit elements; (b) forming a second test file comprising the elements of the first test file, less the elements corresponding to configurations forbidden by design rule manuals; (c) trans-forming the second test file by means of a set of logical operations implemented by computing means to obtain a mask file; (d) testing the mask file and, if the test is negative, modifying the design rule manuals; and (e) repeating steps (a) to (d) until the test of step (d) is positive.
    • 一种用于设计适合于形成集成电路的掩模的方法,包括以下步骤:(a)形成包括集成电路元件的一组配置的第一测试文件; (b)形成包括第一测试文件的元素的第二测试文件,少于与设计规则手册禁止的配置相对应的元素; (c)通过由计算装置实现的一组逻辑操作来转换第二测试文件以获得掩模文件; (d)测试掩模文件,如果测试为负,修改设计规则手册; 和(e)重复步骤(a)至(d),直到步骤(d)的测试为正。
    • 2. 发明申请
    • METHOD FOR DESIGNING MASKS USED TO FORM ELECTRONIC COMPONENTS
    • 用于设计用于形成电子组件的掩码的方法
    • US20110302539A1
    • 2011-12-08
    • US13117164
    • 2011-05-27
    • Julia Castellan
    • Julia Castellan
    • G06F17/50
    • G06F17/5081G06F2217/12Y02P90/265
    • A method for designing masks adapted to the forming of integrated circuits, including the steps of: (a) forming a first test file including a set of configurations of integrated circuit elements; (b) forming a second test file comprising the elements of the first test file, less the elements corresponding to configurations forbidden by design rule manuals; (c) trans-forming the second test file by means of a set of logical operations implemented by computing means to obtain a mask file; (d) testing the mask file and, if the test is negative, modifying the design rule manuals; and (e) repeating steps (a) to (d) until the test of step (d) is positive.
    • 一种用于设计适合于形成集成电路的掩模的方法,包括以下步骤:(a)形成包括集成电路元件的一组配置的第一测试文件; (b)形成包括第一测试文件的元素的第二测试文件,少于与设计规则手册禁止的配置相对应的元素; (c)通过由计算装置实现的一组逻辑操作来转换第二测试文件以获得掩模文件; (d)测试掩模文件,如果测试为负,修改设计规则手册; 和(e)重复步骤(a)至(d),直到步骤(d)的测试为正。