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1. 发明申请

US20060057764A1 IMAGE SENSOR AND FABRICATING METHOD THEREOF 有权
标题翻译：图像传感器及其制作方法
公开(公告)号：US20060057764A1
公开(公告)日：2006-03-16
申请号：US10711377
申请日：2004-09-15
申请人： Jui-Hsiang Pan , Cheng-Kuang Sun , Kuang-Chih Cheng , Kuang-Shin Lee
发明人： Jui-Hsiang Pan , Cheng-Kuang Sun , Kuang-Chih Cheng , Kuang-Shin Lee
IPC分类号： H01L21/00
CPC分类号： H01L27/14618 , H01L27/14621 , H01L27/14627 , H01L27/14636 , H01L27/1464 , H01L27/14685 , H01L2924/0002 , H01L2924/00
摘要： An image sensor comprising an image sensing device layer, a silicon-on-insulator (SOI) layer, an optical device array and a substrate is provided. The SOI layer has a first surface and a second surface. The image sensing device layer is formed on the first surface of the SOI layer. The optical device array is formed on the second surface of the SOI layer. The substrate is disposed above the second surface of the SOI layer and the optical device array is disposed between the substrate and the SOI layer. An incident light coming from the outside environment, passes through the optical device array and the SOI layer, and is received by sensing devices formed in the image sensing device layer. In this manner, the probability of absorption or reflection of the incident light is reduced. Therefore, the sensing performance and the yield of the image sensor of the present invention is improved.
摘要翻译：提供了包括图像感测装置层，绝缘体上硅（SOI）层，光学装置阵列和基板的图像传感器。 SOI层具有第一表面和第二表面。图像感测装置层形成在SOI层的第一表面上。光学器件阵列形成在SOI层的第二表面上。衬底设置在SOI层的第二表面上方，并且光学器件阵列设置在衬底和SOI层之间。来自外部环境的入射光通过光学器件阵列和SOI层，并且由形成在图像感测器件层中的感测器件接收。以这种方式，入射光的吸收或反射的概率降低。因此，提高了本发明的图像传感器的感测性能和产量。

2. 发明授权

US07060592B2 Image sensor and fabricating method thereof 有权
标题翻译：图像传感器及其制造方法
公开(公告)号：US07060592B2
公开(公告)日：2006-06-13
申请号：US10711377
申请日：2004-09-15
申请人： Jui-Hsiang Pan , Cheng-Kuang Sun , Kuang-Chih Cheng , Kuang-Shin Lee
发明人： Jui-Hsiang Pan , Cheng-Kuang Sun , Kuang-Chih Cheng , Kuang-Shin Lee
IPC分类号： H01L21/30 , H01L21/46
CPC分类号： H01L27/14618 , H01L27/14621 , H01L27/14627 , H01L27/14636 , H01L27/1464 , H01L27/14685 , H01L2924/0002 , H01L2924/00
摘要： An image sensor comprising an image sensing device layer, a silicon-on-insulator (SOI) layer, an optical device array and a substrate is provided. The SOI layer has a first surface and a second surface. The image sensing device layer is formed on the first surface of the SOI layer. The optical device array is formed on the second surface of the SOI layer. The substrate is disposed above the second surface of the SOI layer and the optical device array is disposed between the substrate and the SOI layer. An incident light coming from the outside environment, passes through the optical device array and the SOI layer, and is received by sensing devices formed in the image sensing device layer. In this manner, the probability of absorption or reflection of the incident light is reduced. Therefore, the sensing performance and the yield of the image sensor of the present invention is improved.
摘要翻译：提供了包括图像感测装置层，绝缘体上硅（SOI）层，光学装置阵列和基板的图像传感器。 SOI层具有第一表面和第二表面。图像感测装置层形成在SOI层的第一表面上。光学器件阵列形成在SOI层的第二表面上。衬底设置在SOI层的第二表面上方，并且光学器件阵列设置在衬底和SOI层之间。来自外部环境的入射光通过光学器件阵列和SOI层，并且由形成在图像感测器件层中的感测器件接收。以这种方式，入射光的吸收或反射的概率降低。因此，提高了本发明的图像传感器的感测性能和产量。

3. 发明申请

US20060180860A1 IMAGE SENSOR 审中-公开
标题翻译：图像传感器
公开(公告)号：US20060180860A1
公开(公告)日：2006-08-17
申请号：US11308330
申请日：2006-03-16
申请人： Jui-Hsiang Pan , Cheng-Kuang Sun , Kuang-Chih Cheng , Kuang-Hsing Lee
发明人： Jui-Hsiang Pan , Cheng-Kuang Sun , Kuang-Chih Cheng , Kuang-Hsing Lee
IPC分类号： H01L27/12
CPC分类号： H01L27/14618 , H01L27/14621 , H01L27/14627 , H01L27/14636 , H01L27/1464 , H01L27/14685 , H01L2924/0002 , H01L2924/00
摘要： An image sensor including an image sensing device layer, a silicon-on-insulator (SOI) layer, an optical device array and a substrate is provided. The SOI layer has a first surface and a second surface. The image sensing device layer is formed on the first surface of the SOI layer. The optical device array is formed on the second surface of the SOI layer. The substrate is disposed above the second surface of the SOI layer; the optical device array is disposed between the substrate and the SOI layer. An incident light coming from the outside environment, passes through the optical device array and the SOI layer, and is received by sensing devices formed in the image sensing device layer. In this manner, the probability of absorption or reflection of the incident light is reduced. Therefore, the sensing performance and the yield of the image sensor of the present invention is improved.
摘要翻译：提供了包括图像感测装置层，绝缘体上硅层（SOI）层，光学装置阵列和基板的图像传感器。 SOI层具有第一表面和第二表面。图像感测装置层形成在SOI层的第一表面上。光学器件阵列形成在SOI层的第二表面上。衬底设置在SOI层的第二表面上方; 光学器件阵列设置在衬底和SOI层之间。来自外部环境的入射光通过光学器件阵列和SOI层，并且由形成在图像感测器件层中的感测器件接收。以这种方式，入射光的吸收或反射的概率降低。因此，提高了本发明的图像传感器的感测性能和产量。

4. 发明授权

US07531381B2 Manufacturing method of a quad flat no-lead package structure 有权
标题翻译：四边形无引线封装结构的制造方法
公开(公告)号：US07531381B2
公开(公告)日：2009-05-12
申请号：US11307872
申请日：2006-02-26
申请人： Jui-Hsiang Pan , Kuang-Shin Lee , Cheng-Kuang Sun
发明人： Jui-Hsiang Pan , Kuang-Shin Lee , Cheng-Kuang Sun
IPC分类号： H01L21/00
CPC分类号： H01L23/49827 , H01L24/45 , H01L24/48 , H01L2224/05571 , H01L2224/05573 , H01L2224/16 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H01L2924/14 , H01L2924/181 , H01L2924/00 , H01L2224/05599 , H01L2924/00012
摘要： The present invention provides a method for fabricating a quad flat no-lead package structure, comprising a chip carrier and at least a chip. The chip is disposed on the top surface of the chip carrier, while the back surface of the chip carrier includes a plurality of flat no-lead conductive leads as I/O pads of the chip carrier for the external circuitry. A plurality of pads, corresponding to bonding pads of the chip, is disposed on the top surface of the chip carrier. The aforementioned package structure can employ wiring bonding technology, flip chip technology or surface mount technology to attach the chip to the chip carrier.
摘要翻译：本发明提供一种制造四边形扁平无引线封装结构的方法，其包括芯片载体和至少芯片。芯片设置在芯片载体的顶表面上，而芯片载体的背面包括多个平坦的无导线导线作为用于外部电路的芯片载体的I / O焊盘。对应于芯片的接合焊盘的多个焊盘设置在芯片载体的顶表面上。上述封装结构可以采用布线接合技术，倒装芯片技术或表面贴装技术将芯片附接到芯片载体。

5. 发明申请

US20050073055A1 [QUAD FLAT NO-LEAD PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF] 有权
标题翻译： [四边形无铅包装结构及其制造方法]
公开(公告)号：US20050073055A1
公开(公告)日：2005-04-07
申请号：US10710933
申请日：2004-08-13
申请人： Jui-Hsiang Pan , Kuang-Shin Lee , Cheng-Kuang Sun
发明人： Jui-Hsiang Pan , Kuang-Shin Lee , Cheng-Kuang Sun
IPC分类号： H01L23/498 , H01L21/48 , H01L23/053
CPC分类号： H01L23/49827 , H01L24/45 , H01L24/48 , H01L2224/05571 , H01L2224/05573 , H01L2224/16 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H01L2924/14 , H01L2924/181 , H01L2924/00 , H01L2224/05599 , H01L2924/00012
摘要： The present invention provides a QFN package structure, comprising a chip carrier and at least a chip. The chip is disposed on the top surface of the chip carrier, while the back surface of the chip carrier includes a plurality of flat no-lead conductive leads as I/O pads of the chip carrier for the external circuitry. A plurality of pads, corresponding to bonding pads of the chip, is disposed on the top surface of the chip carrier. The aforementioned package structure can employ wiring bonding technology, flip chip technology or surface mount technology to attach the chip to the chip carrier.
摘要翻译：本发明提供一种包括芯片载体和至少芯片的QFN封装结构。芯片设置在芯片载体的顶表面上，而芯片载体的背面包括多个平坦的无引线导线作为用于外部电路的芯片载体的I / O焊盘。对应于芯片的接合焊盘的多个焊盘设置在芯片载体的顶表面上。上述封装结构可以采用布线接合技术，倒装芯片技术或表面贴装技术将芯片附接到芯片载体。

6. 发明申请

US20060131723A1 MANUFACTURING METHOD OF A QUAD FLAT NO-LEAD PACKAGE STRUCTURE 有权
标题翻译：四边形无铅包装结构的制造方法
公开(公告)号：US20060131723A1
公开(公告)日：2006-06-22
申请号：US11307872
申请日：2006-02-26
申请人： Jui-Hsiang Pan , Kuang-Shin Lee , Cheng-Kuang Sun
发明人： Jui-Hsiang Pan , Kuang-Shin Lee , Cheng-Kuang Sun
IPC分类号： H01L23/48
CPC分类号： H01L23/49827 , H01L24/45 , H01L24/48 , H01L2224/05571 , H01L2224/05573 , H01L2224/16 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H01L2924/14 , H01L2924/181 , H01L2924/00 , H01L2224/05599 , H01L2924/00012
摘要： The present invention provides a method for fabricating a quad flat no-lead package structure, comprising a chip carrier and at least a chip. The chip is disposed on the top surface of the chip carrier, while the back surface of the chip carrier includes a plurality of flat no-lead conductive leads as I/O pads of the chip carrier for the external circuitry. A plurality of pads, corresponding to bonding pads of the chip, is disposed on the top surface of the chip carrier. The aforementioned package structure can employ wiring bonding technology, flip chip technology or surface mount technology to attach the chip to the chip carrier.
摘要翻译：本发明提供一种制造四边形扁平无引线封装结构的方法，其包括芯片载体和至少芯片。芯片设置在芯片载体的顶表面上，而芯片载体的背面包括多个平坦的无引线导线作为用于外部电路的芯片载体的I / O焊盘。对应于芯片的接合焊盘的多个焊盘设置在芯片载体的顶表面上。上述封装结构可以采用布线接合技术，倒装芯片技术或表面贴装技术将芯片附接到芯片载体。

7. 发明申请

US20050074916A1 Process for manufacturing semiconductor device 有权
公开(公告)号：US20050074916A1
公开(公告)日：2005-04-07
申请号：US10681458
申请日：2003-10-07
申请人： Cheng-Kuang Sun , Kuang-Shin Lee , Jui-Hsiang Pan
发明人： Cheng-Kuang Sun , Kuang-Shin Lee , Jui-Hsiang Pan
IPC分类号： H01L21/00 , H01L27/146
CPC分类号： H01L27/14632 , H01L27/14601 , H01L27/14623 , H01L27/14625 , H01L27/14636 , H01L2224/48091 , H01L2224/73265 , H01L2924/13091 , H01L2924/00014 , H01L2924/00
摘要： A process for fabricating a semiconductor device is provided. The process integrates a cutting film process into the front-end of semiconductor process. The cutting film is directly formed on the curved surface of the micro-lens or a passivation layer is formed on the micro-lens before covering the passivation layer with the cutting film. In addition to micro-particle contamination due to sawing, the process is able to simplify chip packaging and reduce the size of a photosensitive module.

8. 发明授权

US07291908B2 Quad flat no-lead package structure and manufacturing method thereof 有权
标题翻译：四边形无铅封装结构及其制造方法
公开(公告)号：US07291908B2
公开(公告)日：2007-11-06
申请号：US10710933
申请日：2004-08-13
申请人： Jui-Hsiang Pan , Kuang-Shin Lee , Cheng-Kuang Sun
发明人： Jui-Hsiang Pan , Kuang-Shin Lee , Cheng-Kuang Sun
IPC分类号： H01L23/485
CPC分类号： H01L23/49827 , H01L24/45 , H01L24/48 , H01L2224/05571 , H01L2224/05573 , H01L2224/16 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H01L2924/14 , H01L2924/181 , H01L2924/00 , H01L2224/05599 , H01L2924/00012
摘要： The present invention provides a QFN package structure, comprising a chip carrier and at least a chip. The chip is disposed on the top surface of the chip carrier, while the back surface of the chip carrier includes a plurality of flat no-lead conductive leads as I/O pads of the chip carrier for the external circuitry. A plurality of pads, corresponding to bonding pads of the chip, is disposed on the top surface of the chip carrier. The aforementioned package structure can employ wiring bonding technology, flip chip technology or surface mount technology to attach the chip to the chip carrier.
摘要翻译：本发明提供一种包括芯片载体和至少芯片的QFN封装结构。芯片设置在芯片载体的顶表面上，而芯片载体的背面包括多个平坦的无引线导线作为用于外部电路的芯片载体的I / O焊盘。对应于芯片的接合焊盘的多个焊盘设置在芯片载体的顶表面上。上述封装结构可以采用布线接合技术，倒装芯片技术或表面贴装技术将芯片附接到芯片载体。

9. 发明授权

US06921681B2 Process for manufacturing photosensitive module 有权
标题翻译：光敏模块制造工艺
公开(公告)号：US06921681B2
公开(公告)日：2005-07-26
申请号：US10681458
申请日：2003-10-07
申请人： Cheng-Kuang Sun , Kuang-Shin Lee , Jui-Hsiang Pan
发明人： Cheng-Kuang Sun , Kuang-Shin Lee , Jui-Hsiang Pan
IPC分类号： H01L21/00 , H01L27/146
CPC分类号： H01L27/14632 , H01L27/14601 , H01L27/14623 , H01L27/14625 , H01L27/14636 , H01L2224/48091 , H01L2224/73265 , H01L2924/13091 , H01L2924/00014 , H01L2924/00
摘要： A process for fabricating a semiconductor device is provided. The process integrates a cutting film process into the front-end of semiconductor process. The cutting film is directly formed on the curved surface of the micro-lens or a passivation layer is formed on the micro-lens before covering the passivation layer with the cutting film. In addition to micro-particle contamination due to sawing, the process is able to simplify chip packaging and reduce the size of a photosensitive module.
摘要翻译：提供一种制造半导体器件的工艺。该工艺将切割膜工艺整合到半导体工艺的前端。切割膜直接形成在微透镜的曲面上，或者在用切割膜覆盖钝化层之前，在微透镜上形成钝化层。除了由锯切引起的微粒子污染之外，该工艺还能够简化芯片封装并减小感光模块的尺寸。

10. 发明申请

US20050095739A1 Process for manufacturing semiconductor device 有权
标题翻译：半导体器件制造工艺
公开(公告)号：US20050095739A1
公开(公告)日：2005-05-05
申请号：US10984532
申请日：2004-11-08
申请人： Cheng-Kuang Sun , Kuang-Shin Lee , Jui-Hsiang Pan
发明人： Cheng-Kuang Sun , Kuang-Shin Lee , Jui-Hsiang Pan
IPC分类号： H01L21/00 , H01L27/146
CPC分类号： H01L27/14632 , H01L27/14601 , H01L27/14623 , H01L27/14625 , H01L27/14636 , H01L2224/48091 , H01L2224/73265 , H01L2924/13091 , H01L2924/00014 , H01L2924/00
摘要： A process for fabricating a semiconductor device is provided. The process integrates a cutting film process into the front-end of semiconductor process. The cutting film is directly formed on the curved surface of the micro-lens or a passivation layer is formed on the micro-lens before covering the passivation layer with the cutting film. In addition to micro-particle contamination due to sawing, the process is able to simplify chip packaging and reduce the size of a photosensitive module.
摘要翻译：提供一种制造半导体器件的工艺。该工艺将切割膜工艺整合到半导体工艺的前端。切割膜直接形成在微透镜的曲面上，或者在用切割膜覆盖钝化层之前，在微透镜上形成钝化层。除了由锯切引起的微粒子污染之外，该工艺还能够简化芯片封装并减小感光模块的尺寸。

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